rocket-chip/src/main/scala/coreplex/ResetVector.scala

// See LICENSE.SiFive for license details.

package freechips.rocketchip.coreplex

import Chisel._

/** A single place for all tiles to find out the reset vector */
trait HasResetVectorWire {
  def resetVectorBits: Int
  val global_reset_vector = Wire(UInt(width = resetVectorBits))
}
tilelink: add mask rom 2017-08-01 06:12:45 +02:00			`// See LICENSE.SiFive for license details.`
Combine Coreplex and System Module Hierarchies (#875) * coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless := and := * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC 2017-07-23 17:31:04 +02:00
			`package freechips.rocketchip.coreplex`

			`import Chisel._`

			`/** A single place for all tiles to find out the reset vector */`
			`trait HasResetVectorWire {`
tile: remove global Field ResetVectorBits Reset vector width is determined by systemBus.busView. Also move some defs from HasCoreParameters to HasTileParameters. 2017-09-02 02:50:54 +02:00			`def resetVectorBits: Int`
Combine Coreplex and System Module Hierarchies (#875) * coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless := and := * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC 2017-07-23 17:31:04 +02:00			`val global_reset_vector = Wire(UInt(width = resetVectorBits))`
			`}`