2014-09-01 05:26:55 +02:00
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#--------------------------------------------------------------------
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# Sources
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#--------------------------------------------------------------------
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# Verilog sources
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2016-08-19 18:46:43 +02:00
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bb_vsrcs = $(base_dir)/vsrc/DebugTransportModuleJtag.v \
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$(base_dir)/vsrc/jtag_vpi.v \
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$(base_dir)/vsrc/AsyncMailbox.v
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2014-09-01 05:26:55 +02:00
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sim_vsrcs = \
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2014-09-12 07:11:58 +02:00
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$(generated_dir)/$(MODEL).$(CONFIG).v \
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$(generated_dir)/consts.$(CONFIG).vh \
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2016-08-19 18:46:43 +02:00
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$(base_dir)/vsrc/$(TB).v \
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2016-08-16 07:03:03 +02:00
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$(base_dir)/vsrc/SimDTM.v \
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2016-08-19 18:46:43 +02:00
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$(bb_vsrcs)
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2014-09-01 05:26:55 +02:00
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# C sources
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sim_csrcs = \
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2016-08-16 07:03:03 +02:00
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$(base_dir)/csrc/SimDTM.cc \
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2016-08-19 18:46:43 +02:00
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$(base_dir)/csrc/jtag_vpi.c
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2014-09-01 05:26:55 +02:00
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2014-09-04 18:49:57 +02:00
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#--------------------------------------------------------------------
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# Build Verilog
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#--------------------------------------------------------------------
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verilog: $(sim_vsrcs)
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.PHONY: verilog
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2014-09-01 05:26:55 +02:00
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#--------------------------------------------------------------------
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# Build rules
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#--------------------------------------------------------------------
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VCS = vcs -full64
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2014-09-25 15:43:03 +02:00
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VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
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2014-09-01 05:26:55 +02:00
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+rad +v2k +vcs+lic+wait \
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+vc+list -CC "-I$(VCS_HOME)/include" \
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-CC "-I$(RISCV)/include" \
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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2015-11-06 01:42:05 +01:00
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-CC "-include $(consts_header)" \
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2014-09-01 05:26:55 +02:00
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$(RISCV)/lib/libfesvr.so \
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2016-06-24 05:54:07 +02:00
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-sverilog \
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2015-10-31 05:14:33 +01:00
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+incdir+$(generated_dir) \
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2016-08-19 23:44:48 +02:00
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+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
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2016-04-02 01:40:13 +02:00
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+define+PRINTF_COND=$(TB).printf_cond \
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2016-08-16 07:03:03 +02:00
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+define+STOP_COND=!$(TB).reset \
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2016-08-29 21:29:01 +02:00
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+define+RANDOMIZE_MEM_INIT \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN \
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2014-09-01 05:26:55 +02:00
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+libext+.v \
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2016-08-19 18:46:43 +02:00
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VCS_OPTS += +vpi
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VCS_OPTS += -P $(base_dir)/vsrc/jtag_vpi.tab
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VCS_OPTS += -CC "-DVCS_VPI"
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2014-09-01 05:26:55 +02:00
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#--------------------------------------------------------------------
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# Build the simulator
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#--------------------------------------------------------------------
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2015-07-28 09:23:31 +02:00
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simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
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2016-08-16 07:03:03 +02:00
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$(simv) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
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2014-09-01 05:26:55 +02:00
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cd $(sim_dir) && \
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2015-11-06 01:42:05 +01:00
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rm -rf csrc && \
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2014-09-01 05:26:55 +02:00
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$(VCS) $(VCS_OPTS) -o $(simv) \
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2015-06-26 08:17:35 +02:00
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-debug_pp \
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2014-09-01 05:26:55 +02:00
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2015-07-28 09:23:31 +02:00
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simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
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2016-08-16 07:03:03 +02:00
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$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(consts_header)
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2014-09-01 05:26:55 +02:00
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cd $(sim_dir) && \
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2015-11-06 01:42:05 +01:00
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rm -rf csrc && \
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2014-09-01 05:26:55 +02:00
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$(VCS) $(VCS_OPTS) -o $(simv_debug) \
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+define+DEBUG -debug_pp \
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#--------------------------------------------------------------------
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# Run
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#--------------------------------------------------------------------
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seed = $(shell date +%s)
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exec_simv = $(simv) -q +ntb_random_seed_automatic
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exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic
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