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rocket-chip/src/main/scala/uncore/tilelink2/GPIO.scala

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tilelink2: connect abstract register-based modules to TileLink
2016-08-27 00:48:48 +02:00
// See LICENSE for license details.
package uncore.tilelink2
import Chisel._
tilelink2: AddressSet always has an assigned base address The consensus seems to be that TileLink should not be assigning addresses dynamically. The reasons: 1. We can come up with another scheme for assigning addresses that is independent of TileLink. This decoupling is good, because it would allow us to use the same mechanism for different buses in the SoC. 2. The informational flow of addresses is more likely to naturally follow the module hierarchy than the TileLike bus topology. Thus, it seems better to pass address parameterization using Module constructors. 3. Addresses are still checked by TileLink, so using a Module-centric flow for addresses will not pose a correctness concern. 4. An address need only be provided to a slave on its construction and TileLink parameterization spreads this globally. Thus, the burden to manually assign an address is low.
2016-08-31 23:49:18 +02:00
case class GPIOParams(num: Int, address: BigInt)
tilelink2: connect abstract register-based modules to TileLink
2016-08-27 00:48:48 +02:00
trait GPIOBundle
{
val params: GPIOParams
val gpio = UInt(width = params.num)
}
trait GPIOModule extends HasRegMap
{
val params: GPIOParams
val io: GPIOBundle
val state = RegInit(UInt(0))
io.gpio := state
regmap(0 -> Seq(RegField(params.num, state)))
}
// Create a concrete TL2 version of the abstract GPIO slave
class TLGPIO(p: GPIOParams) extends TLRegisterRouter(p.address)(
new TLRegBundle(p, _) with GPIOBundle)(
new TLRegModule(p, _, _) with GPIOModule)
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