30 lines
630 B
Scala
30 lines
630 B
Scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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case class GPIOParams(num: Int, address: Option[BigInt] = None)
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trait GPIOBundle
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{
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val params: GPIOParams
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val gpio = UInt(width = params.num)
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}
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trait GPIOModule extends HasRegMap
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{
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val params: GPIOParams
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val io: GPIOBundle
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val state = RegInit(UInt(0))
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io.gpio := state
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regmap(0 -> Seq(RegField(params.num, state)))
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}
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// Create a concrete TL2 version of the abstract GPIO slave
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class TLGPIO(p: GPIOParams) extends TLRegisterRouter(p.address)(
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new TLRegBundle(p, _) with GPIOBundle)(
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new TLRegModule(p, _, _) with GPIOModule)
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