2012-02-26 02:09:26 +01:00
|
|
|
package rocket
|
|
|
|
|
|
2011-10-26 08:02:47 +02:00
|
|
|
import Chisel._
|
2012-10-08 05:15:54 +02:00
|
|
|
import Node._
|
2011-10-26 08:02:47 +02:00
|
|
|
|
2013-11-25 13:35:15 +01:00
|
|
|
/* Automatically generated by parse-opcodes */
|
|
|
|
|
object Instructions {
|
2013-09-21 15:32:40 +02:00
|
|
|
def JAL = Bits("b?????????????????????????1100111")
|
|
|
|
|
def JALR = Bits("b?????????????????000?????1101111")
|
|
|
|
|
def BEQ = Bits("b?????????????????000?????1100011")
|
|
|
|
|
def BNE = Bits("b?????????????????001?????1100011")
|
|
|
|
|
def BLT = Bits("b?????????????????100?????1100011")
|
|
|
|
|
def BGE = Bits("b?????????????????101?????1100011")
|
|
|
|
|
def BLTU = Bits("b?????????????????110?????1100011")
|
|
|
|
|
def BGEU = Bits("b?????????????????111?????1100011")
|
|
|
|
|
def LUI = Bits("b?????????????????????????0110111")
|
|
|
|
|
def AUIPC = Bits("b?????????????????????????0010111")
|
|
|
|
|
def ADDI = Bits("b?????????????????000?????0010011")
|
2013-11-21 23:44:58 +01:00
|
|
|
def SLLI = Bits("b000000???????????001?????0010011")
|
2013-09-21 15:32:40 +02:00
|
|
|
def SLTI = Bits("b?????????????????010?????0010011")
|
|
|
|
|
def SLTIU = Bits("b?????????????????011?????0010011")
|
|
|
|
|
def XORI = Bits("b?????????????????100?????0010011")
|
|
|
|
|
def SRLI = Bits("b000000???????????101?????0010011")
|
|
|
|
|
def SRAI = Bits("b010000???????????101?????0010011")
|
|
|
|
|
def ORI = Bits("b?????????????????110?????0010011")
|
|
|
|
|
def ANDI = Bits("b?????????????????111?????0010011")
|
|
|
|
|
def ADD = Bits("b0000000??????????000?????0110011")
|
|
|
|
|
def SUB = Bits("b0100000??????????000?????0110011")
|
|
|
|
|
def SLL = Bits("b0000000??????????001?????0110011")
|
|
|
|
|
def SLT = Bits("b0000000??????????010?????0110011")
|
|
|
|
|
def SLTU = Bits("b0000000??????????011?????0110011")
|
|
|
|
|
def XOR = Bits("b0000000??????????100?????0110011")
|
|
|
|
|
def SRL = Bits("b0000000??????????101?????0110011")
|
|
|
|
|
def SRA = Bits("b0100000??????????101?????0110011")
|
|
|
|
|
def OR = Bits("b0000000??????????110?????0110011")
|
|
|
|
|
def AND = Bits("b0000000??????????111?????0110011")
|
|
|
|
|
def ADDIW = Bits("b?????????????????000?????0011011")
|
2013-11-21 23:44:58 +01:00
|
|
|
def SLLIW = Bits("b0000000??????????001?????0011011")
|
2013-09-21 15:32:40 +02:00
|
|
|
def SRLIW = Bits("b0000000??????????101?????0011011")
|
|
|
|
|
def SRAIW = Bits("b0100000??????????101?????0011011")
|
|
|
|
|
def ADDW = Bits("b0000000??????????000?????0111011")
|
|
|
|
|
def SUBW = Bits("b0100000??????????000?????0111011")
|
|
|
|
|
def SLLW = Bits("b0000000??????????001?????0111011")
|
|
|
|
|
def SRLW = Bits("b0000000??????????101?????0111011")
|
|
|
|
|
def SRAW = Bits("b0100000??????????101?????0111011")
|
|
|
|
|
def LB = Bits("b?????????????????000?????0000011")
|
|
|
|
|
def LH = Bits("b?????????????????001?????0000011")
|
|
|
|
|
def LW = Bits("b?????????????????010?????0000011")
|
|
|
|
|
def LD = Bits("b?????????????????011?????0000011")
|
|
|
|
|
def LBU = Bits("b?????????????????100?????0000011")
|
|
|
|
|
def LHU = Bits("b?????????????????101?????0000011")
|
|
|
|
|
def LWU = Bits("b?????????????????110?????0000011")
|
|
|
|
|
def SB = Bits("b?????????????????000?????0100011")
|
|
|
|
|
def SH = Bits("b?????????????????001?????0100011")
|
|
|
|
|
def SW = Bits("b?????????????????010?????0100011")
|
|
|
|
|
def SD = Bits("b?????????????????011?????0100011")
|
2013-11-25 13:35:15 +01:00
|
|
|
def FENCE = Bits("b?????????????????000?????0001111")
|
|
|
|
|
def FENCE_I = Bits("b?????????????????001?????0001111")
|
|
|
|
|
def MUL = Bits("b0000001??????????000?????0110011")
|
|
|
|
|
def MULH = Bits("b0000001??????????001?????0110011")
|
|
|
|
|
def MULHSU = Bits("b0000001??????????010?????0110011")
|
|
|
|
|
def MULHU = Bits("b0000001??????????011?????0110011")
|
|
|
|
|
def DIV = Bits("b0000001??????????100?????0110011")
|
|
|
|
|
def DIVU = Bits("b0000001??????????101?????0110011")
|
|
|
|
|
def REM = Bits("b0000001??????????110?????0110011")
|
|
|
|
|
def REMU = Bits("b0000001??????????111?????0110011")
|
|
|
|
|
def MULW = Bits("b0000001??????????000?????0111011")
|
|
|
|
|
def DIVW = Bits("b0000001??????????100?????0111011")
|
|
|
|
|
def DIVUW = Bits("b0000001??????????101?????0111011")
|
|
|
|
|
def REMW = Bits("b0000001??????????110?????0111011")
|
|
|
|
|
def REMUW = Bits("b0000001??????????111?????0111011")
|
2013-09-21 15:32:40 +02:00
|
|
|
def AMOADD_W = Bits("b00000????????????010?????0101111")
|
|
|
|
|
def AMOXOR_W = Bits("b00100????????????010?????0101111")
|
|
|
|
|
def AMOOR_W = Bits("b01000????????????010?????0101111")
|
|
|
|
|
def AMOAND_W = Bits("b01100????????????010?????0101111")
|
|
|
|
|
def AMOMIN_W = Bits("b10000????????????010?????0101111")
|
|
|
|
|
def AMOMAX_W = Bits("b10100????????????010?????0101111")
|
|
|
|
|
def AMOMINU_W = Bits("b11000????????????010?????0101111")
|
|
|
|
|
def AMOMAXU_W = Bits("b11100????????????010?????0101111")
|
|
|
|
|
def AMOSWAP_W = Bits("b00001????????????010?????0101111")
|
|
|
|
|
def LR_W = Bits("b00010??00000?????010?????0101111")
|
|
|
|
|
def SC_W = Bits("b00011????????????010?????0101111")
|
|
|
|
|
def AMOADD_D = Bits("b00000????????????011?????0101111")
|
|
|
|
|
def AMOXOR_D = Bits("b00100????????????011?????0101111")
|
|
|
|
|
def AMOOR_D = Bits("b01000????????????011?????0101111")
|
|
|
|
|
def AMOAND_D = Bits("b01100????????????011?????0101111")
|
|
|
|
|
def AMOMIN_D = Bits("b10000????????????011?????0101111")
|
|
|
|
|
def AMOMAX_D = Bits("b10100????????????011?????0101111")
|
|
|
|
|
def AMOMINU_D = Bits("b11000????????????011?????0101111")
|
|
|
|
|
def AMOMAXU_D = Bits("b11100????????????011?????0101111")
|
|
|
|
|
def AMOSWAP_D = Bits("b00001????????????011?????0101111")
|
|
|
|
|
def LR_D = Bits("b00010??00000?????011?????0101111")
|
|
|
|
|
def SC_D = Bits("b00011????????????011?????0101111")
|
2013-11-25 13:35:15 +01:00
|
|
|
def SCALL = Bits("b00000000000000000000000001110011")
|
|
|
|
|
def SBREAK = Bits("b00000000000100000000000001110011")
|
|
|
|
|
def SRET = Bits("b10000000000000000000000001110011")
|
|
|
|
|
def CSRRW = Bits("b?????????????????001?????1110011")
|
|
|
|
|
def CSRRS = Bits("b?????????????????010?????1110011")
|
|
|
|
|
def CSRRC = Bits("b?????????????????011?????1110011")
|
|
|
|
|
def CSRRWI = Bits("b?????????????????101?????1110011")
|
|
|
|
|
def CSRRSI = Bits("b?????????????????110?????1110011")
|
|
|
|
|
def CSRRCI = Bits("b?????????????????111?????1110011")
|
2013-09-21 15:32:40 +02:00
|
|
|
def FADD_S = Bits("b0000000??????????????????1010011")
|
|
|
|
|
def FSUB_S = Bits("b0000100??????????????????1010011")
|
|
|
|
|
def FMUL_S = Bits("b0001000??????????????????1010011")
|
|
|
|
|
def FDIV_S = Bits("b0001100??????????????????1010011")
|
|
|
|
|
def FSQRT_S = Bits("b001000000000?????????????1010011")
|
|
|
|
|
def FSGNJ_S = Bits("b0010100??????????000?????1010011")
|
|
|
|
|
def FSGNJN_S = Bits("b0011000??????????000?????1010011")
|
|
|
|
|
def FSGNJX_S = Bits("b0011100??????????000?????1010011")
|
|
|
|
|
def FADD_D = Bits("b0000001??????????????????1010011")
|
|
|
|
|
def FSUB_D = Bits("b0000101??????????????????1010011")
|
|
|
|
|
def FMUL_D = Bits("b0001001??????????????????1010011")
|
|
|
|
|
def FDIV_D = Bits("b0001101??????????????????1010011")
|
|
|
|
|
def FSQRT_D = Bits("b001000100000?????????????1010011")
|
|
|
|
|
def FSGNJ_D = Bits("b0010101??????????000?????1010011")
|
|
|
|
|
def FSGNJN_D = Bits("b0011001??????????000?????1010011")
|
|
|
|
|
def FSGNJX_D = Bits("b0011101??????????000?????1010011")
|
|
|
|
|
def FCVT_L_S = Bits("b010000000000?????????????1010011")
|
|
|
|
|
def FCVT_LU_S = Bits("b010010000000?????????????1010011")
|
|
|
|
|
def FCVT_W_S = Bits("b010100000000?????????????1010011")
|
|
|
|
|
def FCVT_WU_S = Bits("b010110000000?????????????1010011")
|
|
|
|
|
def FCVT_L_D = Bits("b010000100000?????????????1010011")
|
|
|
|
|
def FCVT_LU_D = Bits("b010010100000?????????????1010011")
|
|
|
|
|
def FCVT_W_D = Bits("b010100100000?????????????1010011")
|
|
|
|
|
def FCVT_WU_D = Bits("b010110100000?????????????1010011")
|
|
|
|
|
def FCVT_S_L = Bits("b011000000000?????????????1010011")
|
|
|
|
|
def FCVT_S_LU = Bits("b011010000000?????????????1010011")
|
|
|
|
|
def FCVT_S_W = Bits("b011100000000?????????????1010011")
|
|
|
|
|
def FCVT_S_WU = Bits("b011110000000?????????????1010011")
|
|
|
|
|
def FCVT_D_L = Bits("b011000100000?????????????1010011")
|
|
|
|
|
def FCVT_D_LU = Bits("b011010100000?????????????1010011")
|
|
|
|
|
def FCVT_D_W = Bits("b011100100000?????????????1010011")
|
|
|
|
|
def FCVT_D_WU = Bits("b011110100000?????????????1010011")
|
|
|
|
|
def FCVT_S_D = Bits("b100010000000?????????????1010011")
|
|
|
|
|
def FCVT_D_S = Bits("b100000100000?????????????1010011")
|
|
|
|
|
def FEQ_S = Bits("b1010100??????????000?????1010011")
|
|
|
|
|
def FLT_S = Bits("b1011000??????????000?????1010011")
|
|
|
|
|
def FLE_S = Bits("b1011100??????????000?????1010011")
|
|
|
|
|
def FEQ_D = Bits("b1010101??????????000?????1010011")
|
|
|
|
|
def FLT_D = Bits("b1011001??????????000?????1010011")
|
|
|
|
|
def FLE_D = Bits("b1011101??????????000?????1010011")
|
|
|
|
|
def FMIN_S = Bits("b1100000??????????000?????1010011")
|
|
|
|
|
def FMAX_S = Bits("b1100100??????????000?????1010011")
|
|
|
|
|
def FMIN_D = Bits("b1100001??????????000?????1010011")
|
|
|
|
|
def FMAX_D = Bits("b1100101??????????000?????1010011")
|
|
|
|
|
def FMV_X_S = Bits("b111000000000?????000?????1010011")
|
|
|
|
|
def FMV_X_D = Bits("b111000100000?????000?????1010011")
|
|
|
|
|
def FMV_S_X = Bits("b111100000000?????000?????1010011")
|
|
|
|
|
def FMV_D_X = Bits("b111100100000?????000?????1010011")
|
|
|
|
|
def FLW = Bits("b?????????????????010?????0000111")
|
|
|
|
|
def FLD = Bits("b?????????????????011?????0000111")
|
|
|
|
|
def FSW = Bits("b?????????????????010?????0100111")
|
|
|
|
|
def FSD = Bits("b?????????????????011?????0100111")
|
|
|
|
|
def FMADD_S = Bits("b?????00??????????????????1000011")
|
|
|
|
|
def FMSUB_S = Bits("b?????00??????????????????1000111")
|
|
|
|
|
def FNMSUB_S = Bits("b?????00??????????????????1001011")
|
|
|
|
|
def FNMADD_S = Bits("b?????00??????????????????1001111")
|
|
|
|
|
def FMADD_D = Bits("b?????01??????????????????1000011")
|
|
|
|
|
def FMSUB_D = Bits("b?????01??????????????????1000111")
|
|
|
|
|
def FNMSUB_D = Bits("b?????01??????????????????1001011")
|
|
|
|
|
def FNMADD_D = Bits("b?????01??????????????????1001111")
|
|
|
|
|
def CUSTOM0 = Bits("b?????????????????000?????0001011")
|
|
|
|
|
def CUSTOM0_RS1 = Bits("b?????????????????010?????0001011")
|
|
|
|
|
def CUSTOM0_RS1_RS2 = Bits("b?????????????????011?????0001011")
|
|
|
|
|
def CUSTOM0_RD = Bits("b?????????????????100?????0001011")
|
|
|
|
|
def CUSTOM0_RD_RS1 = Bits("b?????????????????110?????0001011")
|
|
|
|
|
def CUSTOM0_RD_RS1_RS2 = Bits("b?????????????????111?????0001011")
|
|
|
|
|
def CUSTOM1 = Bits("b?????????????????000?????0101011")
|
|
|
|
|
def CUSTOM1_RS1 = Bits("b?????????????????010?????0101011")
|
|
|
|
|
def CUSTOM1_RS1_RS2 = Bits("b?????????????????011?????0101011")
|
|
|
|
|
def CUSTOM1_RD = Bits("b?????????????????100?????0101011")
|
|
|
|
|
def CUSTOM1_RD_RS1 = Bits("b?????????????????110?????0101011")
|
|
|
|
|
def CUSTOM1_RD_RS1_RS2 = Bits("b?????????????????111?????0101011")
|
|
|
|
|
def CUSTOM2 = Bits("b?????????????????000?????1011011")
|
|
|
|
|
def CUSTOM2_RS1 = Bits("b?????????????????010?????1011011")
|
|
|
|
|
def CUSTOM2_RS1_RS2 = Bits("b?????????????????011?????1011011")
|
|
|
|
|
def CUSTOM2_RD = Bits("b?????????????????100?????1011011")
|
|
|
|
|
def CUSTOM2_RD_RS1 = Bits("b?????????????????110?????1011011")
|
|
|
|
|
def CUSTOM2_RD_RS1_RS2 = Bits("b?????????????????111?????1011011")
|
|
|
|
|
def CUSTOM3 = Bits("b?????????????????000?????1111011")
|
|
|
|
|
def CUSTOM3_RS1 = Bits("b?????????????????010?????1111011")
|
|
|
|
|
def CUSTOM3_RS1_RS2 = Bits("b?????????????????011?????1111011")
|
|
|
|
|
def CUSTOM3_RD = Bits("b?????????????????100?????1111011")
|
|
|
|
|
def CUSTOM3_RD_RS1 = Bits("b?????????????????110?????1111011")
|
|
|
|
|
def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011")
|
2013-06-13 19:31:04 +02:00
|
|
|
}
|
2013-11-25 13:35:15 +01:00
|
|
|
object CSRs {
|
|
|
|
|
val sup0 = 1280
|
|
|
|
|
val fflags = 1
|
|
|
|
|
val frm = 2
|
|
|
|
|
val fcsr = 3
|
|
|
|
|
val cycle = 4
|
|
|
|
|
val time = 5
|
|
|
|
|
val instret = 6
|
|
|
|
|
val sup1 = 1281
|
|
|
|
|
val evec = 1288
|
|
|
|
|
val cause = 1289
|
|
|
|
|
val status = 1290
|
|
|
|
|
val hartid = 1291
|
|
|
|
|
val impl = 1292
|
|
|
|
|
val epc = 1282
|
|
|
|
|
val send_ipi = 1294
|
|
|
|
|
val clear_ipi = 1295
|
|
|
|
|
val badvaddr = 1283
|
|
|
|
|
val ptbr = 1284
|
|
|
|
|
val stats = 1308
|
|
|
|
|
val reset = 1309
|
|
|
|
|
val tohost = 1310
|
|
|
|
|
val asid = 1285
|
|
|
|
|
val count = 1286
|
|
|
|
|
val compare = 1287
|
|
|
|
|
val fromhost = 1311
|
|
|
|
|
val fatc = 1293
|
|
|
|
|
val all = {
|
|
|
|
|
val res = collection.mutable.ArrayBuffer[Int]()
|
|
|
|
|
res += sup0
|
|
|
|
|
res += fflags
|
|
|
|
|
res += frm
|
|
|
|
|
res += fcsr
|
|
|
|
|
res += cycle
|
|
|
|
|
res += time
|
|
|
|
|
res += instret
|
|
|
|
|
res += sup1
|
|
|
|
|
res += evec
|
|
|
|
|
res += cause
|
|
|
|
|
res += status
|
|
|
|
|
res += hartid
|
|
|
|
|
res += impl
|
|
|
|
|
res += epc
|
|
|
|
|
res += send_ipi
|
|
|
|
|
res += clear_ipi
|
|
|
|
|
res += badvaddr
|
|
|
|
|
res += ptbr
|
|
|
|
|
res += stats
|
|
|
|
|
res += reset
|
|
|
|
|
res += tohost
|
|
|
|
|
res += asid
|
|
|
|
|
res += count
|
|
|
|
|
res += compare
|
|
|
|
|
res += fromhost
|
|
|
|
|
res += fatc
|
|
|
|
|
res.toArray
|
|
|
|
|
}
|
|
|
|
|
}
|
