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rocket-chip/vsim/Makefrag

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update for rocket-chip release
2014-09-01 05:26:55 +02:00
#--------------------------------------------------------------------
# Sources
#--------------------------------------------------------------------
# Verilog sources
debug: remove old Verilog DebugTransportModuleJtag file as it has been replaced by Chisel version
2017-03-28 06:24:44 +02:00
bb_vsrcs = \
Plusargs -- tilelink timeout detection from the command line (#752) * util: PlusArg gives Chisel access to the command-line * tilelink2: add a progress watchdog to Monitors
2017-05-19 07:49:59 +02:00
$(base_dir)/vsrc/plusarg_reader.v \
ClockDivider2: fix launch alignment of clocks (vcs) Doing this in Chisel leads to non-determinism due to shitty Verilog ordering semantis. Using an '=' ensures that all of the clock posedges fire before concurrent register updates. See "Gotcha 29: Sequential logic that requires blocking assignments" in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
2017-02-17 11:49:35 +01:00
$(base_dir)/vsrc/ClockDivider2.v \
vsrc: add ClockDivider3 used to simulate unaligned clocks
2017-05-14 22:29:36 +02:00
$(base_dir)/vsrc/ClockDivider3.v \
Add missing dependency
2016-09-14 20:50:28 +02:00
$(base_dir)/vsrc/AsyncResetReg.v \
Add JTAG DTM and test support in simulation Initial cut checkpoint which compiles and runs but there is some off-by-1 in the protocol Debugging the clock crossing logic checkpoint which works Clean up the AsyncMailbox black box
2016-08-19 18:46:43 +02:00
update for rocket-chip release
2014-09-01 05:26:55 +02:00
sim_vsrcs = \
[testharness] vsim makefrag cleanup
2016-09-19 22:46:45 +02:00
$(generated_dir)/$(long_name).v \
$(generated_dir)/$(long_name).behav_srams.v \
connect testharness components via member functions (#236) to prevent code duplication for new testbenches
2016-09-02 03:38:39 +02:00
$(base_dir)/vsrc/$(TB).v \
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(base_dir)/vsrc/SimDTM.v \
Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. This is simpler than JTAGVPI and is supported better by Verilor. It is also the same thing Spike uses.
2017-04-12 05:03:34 +02:00
$(base_dir)/vsrc/SimJTAG.v \
Add JTAG DTM and test support in simulation Initial cut checkpoint which compiles and runs but there is some off-by-1 in the protocol Debugging the clock crossing logic checkpoint which works Clean up the AsyncMailbox black box
2016-08-19 18:46:43 +02:00
$(bb_vsrcs)
update for rocket-chip release
2014-09-01 05:26:55 +02:00
# C sources
sim_csrcs = \
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(base_dir)/csrc/SimDTM.cc \
Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. This is simpler than JTAGVPI and is supported better by Verilor. It is also the same thing Spike uses.
2017-04-12 05:03:34 +02:00
$(base_dir)/csrc/SimJTAG.cc \
Remove JTAG vpi from VCS build h/t @mwachs5 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-02-26 21:12:18 +01:00
$(base_dir)/csrc/remote_bitbang.cc
update for rocket-chip release
2014-09-01 05:26:55 +02:00
fix problem introduced with verilog generation in vsim/fsim
2014-09-04 18:49:57 +02:00
#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------
verilog: $(sim_vsrcs)
.PHONY: verilog
update for rocket-chip release
2014-09-01 05:26:55 +02:00
#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------
VCS = vcs -full64
error out for PCWM-L, port width mismatch
2014-09-25 15:43:03 +02:00
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
+rad +v2k +vcs+lic+wait \
+vc+list -CC "-I$(VCS_HOME)/include" \
-CC "-I$(RISCV)/include" \
-CC "-std=c++11" \
-CC "-Wl,-rpath,$(RISCV)/lib" \
$(RISCV)/lib/libfesvr.so \
Exit from testbench, not C code Otherwise, we don't get coverage data from the simulator.
2016-06-24 05:54:07 +02:00
-sverilog \
add multichannel NASTI support in Verilog testbench
2015-10-31 05:14:33 +01:00
+incdir+$(generated_dir) \
make CLOCK_PERIOD actually be the clock period, instead of half of the clock period
2016-08-19 23:44:48 +02:00
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
Disable printf/assert during reset
2016-04-02 01:40:13 +02:00
+define+PRINTF_COND=$(TB).printf_cond \
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
+define+STOP_COND=!$(TB).reset \
Get in line with FIRRTL randomization flag changes (#231)
2016-08-29 21:29:01 +02:00
+define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
+libext+.v \
#--------------------------------------------------------------------
# Build the simulator
#--------------------------------------------------------------------
[testharness] vsim makefrag cleanup
2016-09-19 22:46:45 +02:00
simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
Artefact output (#545) * build: stop using empty .prm file * generator: general-purpose mechanism for creating elaboration artefacts
2017-02-03 04:24:55 +01:00
$(simv) : $(sim_vsrcs) $(sim_csrcs)
update for rocket-chip release
2014-09-01 05:26:55 +02:00
cd $(sim_dir) && \
no spaces in Makefrag
2015-11-06 01:42:05 +01:00
rm -rf csrc && \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
$(VCS) $(VCS_OPTS) -o $(simv) \
Massive update containing several months of changes from the now-defunct private chip repo. * Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API. * Additional tests. * New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit * Updated TileLink protocol, NASTI protocol SHIMs. * Lays groundwork for multiple top-level memory channels, superscalar fetch. * Bump all submodules.
2015-06-26 08:17:35 +02:00
-debug_pp \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
[testharness] vsim makefrag cleanup
2016-09-19 22:46:45 +02:00
simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
Artefact output (#545) * build: stop using empty .prm file * generator: general-purpose mechanism for creating elaboration artefacts
2017-02-03 04:24:55 +01:00
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
update for rocket-chip release
2014-09-01 05:26:55 +02:00
cd $(sim_dir) && \
no spaces in Makefrag
2015-11-06 01:42:05 +01:00
rm -rf csrc && \
update for rocket-chip release
2014-09-01 05:26:55 +02:00
$(VCS) $(VCS_OPTS) -o $(simv_debug) \
+define+DEBUG -debug_pp \
#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------
seed = $(shell date +%s)
Fix VCS argument parsing (#1266) * Add +permissive/+permissive-off for VCS args This adds guards around Verilog/VCS options for VCS calls with HTIF's new `+permissive`/`+permissive-off` options. This enables HTIF to permissively parse all options inside one of these guards while not erroring on unknonw commands. This is necessary for VCS, unlike with the emulator, as HTIF is giving all commands as opposed to only host and target arguments (like with Verilator/emulator.cc). * Bump riscv-tools for fesvr VCS fix * Bump riscv-rools/riscv-fesvr (VCS stderr fix) Fixes #1266 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-08 07:59:04 +01:00
exec_simv = $(simv) +permissive -q +ntb_random_seed_automatic +permissive-off
exec_simv_debug = $(simv_debug) +permissive -q +ntb_random_seed_automatic +permissive-off
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