Richard Xia f4375c2266 Add variable to control what program gets flashed to FPGA.

2016-12-08 12:14:17 -08:00

..

constrs

Initial commit.

2016-11-29 05:23:11 -08:00

script

Remove verilog header files built from Chisel .prm file.

2016-11-30 14:30:05 -08:00

src

Remove verilog header files built from Chisel .prm file.

2016-11-30 14:30:05 -08:00

.gitignore

Initial commit.

2016-11-29 05:23:11 -08:00

Makefile

Add variable to control what program gets flashed to FPGA.

2016-12-08 12:14:17 -08:00