96 lines
3.4 KiB
Markdown
96 lines
3.4 KiB
Markdown
Freedom
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=======
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This repository contains the RTL created by SiFive for its Freedom E300 and U500
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platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300
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Platform and is designed to be mapped onto an [Arty FPGA Evaluation
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Kit](https://www.xilinx.com/products/boards-and-kits/arty.html). The Freedom
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U500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed to
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be mapped onto a [VC707 FPGA Evaluation
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Kit](https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html).
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Both systems boot autonomously and can be controlled via an external debugger.
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Please read the section corresponding to the kit you are interested in for
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instructions on how to use this repo.
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Software Requirement
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--------------------
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To compile the bootloaders for both Freedom E300 Arty and U500 VC707
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FPGA dev kits, the RISC-V software toolchain must be installed locally and
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set the $(RISCV) environment variable to point to the location of where the
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RISC-V toolchains are installed. You can build the toolchain from scratch
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or download the tools here: https://www.sifive.com/products/tools/
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Freedom E300 Arty FPGA Dev Kit
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------------------------------
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The Freedom E300 Arty FPGA Dev Kit implements a Freedom E300 chip.
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### How to build
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The Makefile corresponding to the Freedom E300 Arty FPGA Dev Kit is
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`Makefile.e300artydevkit` and it consists of two main targets:
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- `verilog`: to compile the Chisel source files and generate the Verilog files.
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- `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
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onto an Arty FPGA board.
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To execute these targets, you can run the following commands:
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```sh
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$ make -f Makefile.e300artydevkit verilog
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$ make -f Makefile.e300artydevkit mcs
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```
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Note: This flow requires Vivado 2017.1. Old versions are known to fail.
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These will place the files under `builds/e300artydevkit/obj`.
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Note that in order to run the `mcs` target, you need to have the `vivado`
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executable on your `PATH`.
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### Bootrom
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The default bootrom consists of a program that immediately jumps to address
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0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty
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board.
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### Using the generated MCS Image
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For instructions for getting the generated image onto an FPGA and programming it with software using the [Freedom E SDK](https://github.com/sifive/freedom-e-sdk), please see the [Freedom E310 Arty FPGA Dev Kit Getting Started Guide](https://www.sifive.com/documentation/freedom-soc/freedom-e300-arty-fpga-dev-kit-getting-started-guide/).
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Freedom U500 VC707 FPGA Dev Kit
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-------------------------------
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The Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 platform.
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### How to build
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The Makefile corresponding to the Freedom U500 VC707 FPGA Dev Kit is
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`Makefile.u500vc707devkit` and it consists of two main targets:
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- `verilog`: to compile the Chisel source files and generate the Verilog files.
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- `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
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onto an VC707 FPGA board.
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To execute these targets, you can run the following commands:
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```sh
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$ make -f Makefile.u500vc707devkit verilog
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$ make -f Makefile.u500vc707devkit mcs
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```
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Note: This flow requires Vivado 2016.4. Newer versions are known to fail.
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These will place the files under `builds/u500vc707devkit/obj`.
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Note that in order to run the `mcs` target, you need to have the `vivado`
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executable on your `PATH`.
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### Bootrom
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The default bootrom consists of a bootloader that loads a program off the SD
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card slot on the VC707 board.
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