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2 changed files with 3 additions and 5 deletions

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@ -34,8 +34,6 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
// DUT
//-----------------------------------------------------------------------
// Connect the clock to the 50 Mhz output from the PLL
dut_clock := clk50
withClockAndReset(dut_clock, dut_reset) {
val dut = Module(LazyModule(new U500ML507DevKitSystem).module)

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@ -46,10 +46,10 @@ class TLMemoryML507(c: MemoryML507Params)(implicit p: Parameters) extends LazyMo
val (in, edge)= node.in(0)
// Tie off unused channels
in.a.ready := Bool(true)
in.a.ready := Bool(false)
in.b.valid := Bool(false)
in.c.ready := Bool(true)
in.c.ready := Bool(false)
in.d.valid := Bool(false)
in.e.ready := Bool(true)
in.e.ready := Bool(false)
}
}