src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala

@@ -34,6 +34,8 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
   // DUT
   //-----------------------------------------------------------------------
 
+  // Connect the clock to the 50 Mhz output from the PLL
+  dut_clock := clk50
   withClockAndReset(dut_clock, dut_reset) {
     val dut = Module(LazyModule(new U500ML507DevKitSystem).module)
 

src/main/scala/unleashed/u500ml507devkit/fpga/Memory.scala

@@ -46,10 +46,10 @@ class TLMemoryML507(c: MemoryML507Params)(implicit p: Parameters) extends LazyMo
         val (in, edge)= node.in(0)
 
         // Tie off unused channels
-        in.a.ready := Bool(false)
+        in.a.ready := Bool(true)
         in.b.valid := Bool(false)
-        in.c.ready := Bool(false)
+        in.c.ready := Bool(true)
         in.d.valid := Bool(false)
-        in.e.ready := Bool(false)
+        in.e.ready := Bool(true)
     }
 }