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base: riscv:1cb558d2ea5ee92be947aa442d0dc746966df7a7
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riscv:ml507
riscv:boot-test
riscv:master
..
compare: riscv:c10d2378e7de8cfed92d5c015a9d4f283b4e8850
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riscv:ml507
riscv:boot-test
riscv:master

No commits in common. "1cb558d2ea5ee92be947aa442d0dc746966df7a7" and "c10d2378e7de8cfed92d5c015a9d4f283b4e8850" have entirely different histories.
1cb558d2ea ... c10d2378e7

2 changed files with 5 additions and 3 deletions
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2
src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala
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@ -34,6 +34,8 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
// DUT // DUT
//----------------------------------------------------------------------- //-----------------------------------------------------------------------
// Connect the clock to the 50 Mhz output from the PLL
dut_clock := clk50
withClockAndReset(dut_clock, dut_reset) { withClockAndReset(dut_clock, dut_reset) {
val dut = Module(LazyModule(new U500ML507DevKitSystem).module) val dut = Module(LazyModule(new U500ML507DevKitSystem).module)

6
src/main/scala/unleashed/u500ml507devkit/fpga/Memory.scala
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@ -46,10 +46,10 @@ class TLMemoryML507(c: MemoryML507Params)(implicit p: Parameters) extends LazyMo
val (in, edge)= node.in(0) val (in, edge)= node.in(0)
// Tie off unused channels // Tie off unused channels
in.a.ready := Bool(false) in.a.ready := Bool(true)
in.b.valid := Bool(false) in.b.valid := Bool(false)
in.c.ready := Bool(false) in.c.ready := Bool(true)
in.d.valid := Bool(false) in.d.valid := Bool(false)
in.e.ready := Bool(false) in.e.ready := Bool(true)
} }
} }