riscv/freedom
1
0 Fork 0
Code Issues Releases Activity

Remove verilog header files built from Chisel .prm file.

Browse Source
This commit is contained in:
Richard Xia committed 2016-11-30 14:30:05 -08:00
1 parent 275e2cd693
commit c14985f3a7
7 files changed
+7 -30
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

fpga/u500vc707devkit/Makefile
+1 -1
View File
@@ -6,7 +6,7 @@ VIVADOFLAGS := \
bit := obj/system.bit
$(bit): script/impl.tcl script/init.tcl
VSRC_TOP=$(VSRC_TOP) VSRC_CONSTS=$(VSRC_CONSTS) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
VSRC_TOP=$(VSRC_TOP) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
.PHONY: bit
bit: $(bit)