Remove verilog header files built from Chisel .prm file.

2016-11-30 14:30:05 -08:00
parent 275e2cd693
commit c14985f3a7
7 changed files with 7 additions and 30 deletions
--- a/fpga/e300artydevkit/script/prologue.tcl
+++ b/fpga/e300artydevkit/script/prologue.tcl
@ -50,15 +50,10 @@ if {[info exists ::env(EXTRA_VSRCS)]} {
 #}

 set vsrc_top $::env(VSRC_TOP)
-set vsrc_consts $::env(VSRC_CONSTS)

-set_property verilog_define [list \
-                                 "VSRC_CONSTS=${vsrc_consts}" \
-                                 "VSRC_TOP=${vsrc_top}" \
-                                ] $obj
+set_property verilog_define [list "VSRC_TOP=${vsrc_top}"] $obj

 add_files -norecurse -fileset $obj $vsrc_top
-add_files -norecurse -fileset $obj $vsrc_consts

 if {[get_filesets -quiet sim_1] eq ""} {
  create_fileset -simset sim_1