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Remove verilog header files built from Chisel .prm file.

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This commit is contained in:
Richard Xia
2016-11-30 14:30:05 -08:00
parent 275e2cd693
commit c14985f3a7
7 changed files with 7 additions and 30 deletions
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2
fpga/e300artydevkit/Makefile
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@ -6,7 +6,7 @@ VIVADOFLAGS := \
bit := obj/system.bit
$(bit): script/impl.tcl script/init.tcl
VSRC_TOP=$(VSRC_TOP) VSRC_CONSTS=$(VSRC_CONSTS) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
VSRC_TOP=$(VSRC_TOP) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
.PHONY: bit
bit: $(bit)