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Remove verilog header files built from Chisel .prm file.

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This commit is contained in:
Richard Xia
2016-11-30 14:30:05 -08:00
parent 275e2cd693
commit c14985f3a7
7 changed files with 7 additions and 30 deletions
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2
fpga/e300artydevkit/Makefile
View File

@ -6,7 +6,7 @@ VIVADOFLAGS := \
bit := obj/system.bit
$(bit): script/impl.tcl script/init.tcl
VSRC_TOP=$(VSRC_TOP) VSRC_CONSTS=$(VSRC_CONSTS) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
VSRC_TOP=$(VSRC_TOP) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
.PHONY: bit
bit: $(bit)

7
fpga/e300artydevkit/script/prologue.tcl
View File

@ -50,15 +50,10 @@ if {[info exists ::env(EXTRA_VSRCS)]} {
#}
set vsrc_top $::env(VSRC_TOP)
set vsrc_consts $::env(VSRC_CONSTS)
set_property verilog_define [list \
"VSRC_CONSTS=${vsrc_consts}" \
"VSRC_TOP=${vsrc_top}" \
] $obj
set_property verilog_define [list "VSRC_TOP=${vsrc_top}"] $obj
add_files -norecurse -fileset $obj $vsrc_top
add_files -norecurse -fileset $obj $vsrc_consts
if {[get_filesets -quiet sim_1] eq ""} {
create_fileset -simset sim_1

3
fpga/e300artydevkit/src/system.v
View File

@ -1,8 +1,5 @@
`timescale 1ns/1ps
`define STRINGIFY(x) `"x`"
`include `STRINGIFY(`VSRC_CONSTS)
module system
(
input wire CLK100MHZ,