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Remove verilog header files built from Chisel .prm file.

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This commit is contained in:
Richard Xia
2016-11-30 14:30:05 -08:00
parent 275e2cd693
commit c14985f3a7
7 changed files with 7 additions and 30 deletions
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13
common.mk
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@ -47,20 +47,13 @@ ifneq ($(PATCHVERILOG),"")
endif
verilog_consts_vh := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vh
$(verilog_consts_vh): $(firrtl_prm)
echo "\`ifndef CONST_VH" > $@
echo "\`define CONST_VH" >> $@
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $< >> $@
echo "\`endif // CONST_VH" >> $@
.PHONY: verilog
verilog: $(verilog) $(verilog_consts_vh)
verilog: $(verilog)
# Build .mcs
mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
$(mcs): $(verilog) $(verilog_consts_vh)
VSRC_TOP=$(verilog) VSRC_CONSTS=$(verilog_consts_vh) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
$(mcs): $(verilog)
VSRC_TOP=$(verilog) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
cp $(FPGA_DIR)/obj/system.mcs $@
.PHONY: mcs