Merge pull request #47 from sifive/bump-repos

build: update all submodules to their current master

Makefile.e300artydevkit

@@ -4,7 +4,7 @@ BUILD_DIR := $(base_dir)/builds/e300artydevkit
 FPGA_DIR := $(base_dir)/fpga-shells/xilinx
 MODEL := E300ArtyDevKitFPGAChip
 PROJECT := sifive.freedom.everywhere.e300artydevkit
-CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
+export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
 export CONFIG := E300ArtyDevKitConfig
 export BOARD := arty
 export BOOTROM_DIR := $(base_dir)/bootrom/xip

Makefile.u500vc707devkit

@@ -4,7 +4,7 @@ BUILD_DIR := $(base_dir)/builds/u500vc707devkit
 FPGA_DIR := $(base_dir)/fpga-shells/xilinx
 MODEL := U500VC707DevKitFPGAChip
 PROJECT := sifive.freedom.unleashed.u500vc707devkit
-CONFIG_PROJECT := sifive.freedom.unleashed.u500vc707devkit
+export CONFIG_PROJECT := sifive.freedom.unleashed.u500vc707devkit
 export CONFIG := U500VC707DevKitConfig
 export BOARD := vc707
 export BOOTROM_DIR := $(base_dir)/bootrom/sdboot

bootrom/sdboot/Makefile

@@ -7,8 +7,8 @@ CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0
 CFLAGS+= -I $(BOOTROM_DIR)/include -I.
 LFLAGS=-static -nostdlib -L $(BOOTROM_DIR)/linker -T sdboot.elf.lds
 
-dtb := $(BUILD_DIR)/$(CONFIG).dtb
+dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb
-$(dtb): $(BUILD_DIR)/$(CONFIG).dts
+$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts
 	dtc -I dts -O dtb -o $@ $<
 
 .PHONY: dtb

bootrom/xip/Makefile

@@ -5,8 +5,8 @@ OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
 CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g
 LFLAGS=-static -nostdlib
 
-dtb := $(BUILD_DIR)/$(CONFIG).dtb
+dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb
-$(dtb): $(BUILD_DIR)/$(CONFIG).dts
+$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts
 	dtc -I dts -O dtb -o $@ $<
 
 .PHONY: dtb

common.mk

@@ -46,7 +46,7 @@ $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.sc
 firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir
 $(firrtl): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
-	$(SBT) "run-main freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
+	$(SBT) "runMain freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
 
 .PHONY: firrtl
 firrtl: $(firrtl)

fpga-shells

@@ -1 +1 @@
-Subproject commit ba7beb676d55b73334bd4a85623e56c713a83773
+Subproject commit 0ca9f2bb66a8987b3334e446c27e05c7c2c6bde9

rocket-chip

@@ -1 +1 @@
-Subproject commit 7e75d63ba6b4c1b50aaaf920e1c693ef6acf51d7
+Subproject commit 8c6e7456531c4d7b846d0532b2b94805b26c9793

sifive-blocks

@@ -1 +1 @@
-Subproject commit 9052a079d404ebbfda5f01765b909c20503504ad
+Subproject commit 6795f401075e2d21166613ff2c1c3a585b2ff1e8

src/main/scala/everywhere/e300artydevkit/Config.scala

@@ -2,7 +2,7 @@
 package sifive.freedom.everywhere.e300artydevkit
 
 import freechips.rocketchip.config._
-import freechips.rocketchip.coreplex._
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}

src/main/scala/everywhere/e300artydevkit/Platform.scala

@@ -4,7 +4,7 @@ package sifive.freedom.everywhere.e300artydevkit
 import Chisel._
 
 import freechips.rocketchip.config._
-import freechips.rocketchip.coreplex._
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._

src/main/scala/everywhere/e300artydevkit/System.scala

@@ -4,7 +4,7 @@ package sifive.freedom.everywhere.e300artydevkit
 import Chisel._
 
 import freechips.rocketchip.config._
-import freechips.rocketchip.coreplex._
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
@@ -21,7 +21,7 @@ import sifive.blocks.devices.i2c._
 // E300ArtyDevKitSystem
 //-------------------------------------------------------------------------
 
-class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketCoreplex
+class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem
     with HasPeripheryMaskROMSlave
     with HasPeripheryDebug
     with HasPeripheryMockAON
@@ -35,7 +35,7 @@ class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketCoreplex
 }
 
 class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L)
-  extends RocketCoreplexModule(_outer)
+  extends RocketSubsystemModuleImp(_outer)
     with HasPeripheryDebugModuleImp
     with HasPeripheryUARTModuleImp
     with HasPeripherySPIModuleImp

src/main/scala/unleashed/u500vc707devkit/Config.scala

@@ -2,7 +2,7 @@
 package sifive.freedom.unleashed.u500vc707devkit
 
 import freechips.rocketchip.config._
-import freechips.rocketchip.coreplex._
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
@@ -26,11 +26,11 @@ class FreedomUVC707Config extends Config(
 // Freedom U500 VC707 Dev Kit Peripherals
 class U500VC707DevKitPeripherals extends Config((site, here, up) => {
   case PeripheryUARTKey => List(
-    UARTParams(address = BigInt(0x54000000L)))
+    UARTParams(address = BigInt(0x64000000L)))
   case PeripherySPIKey => List(
-    SPIParams(rAddress = BigInt(0x54001000L)))
+    SPIParams(rAddress = BigInt(0x64001000L)))
   case PeripheryGPIOKey => List(
-    GPIOParams(address = BigInt(0x54002000L), width = 4))
+    GPIOParams(address = BigInt(0x64002000L), width = 4))
   case PeripheryMaskROMKey => List(
     MaskROMParams(address = 0x10000, name = "BootROM"))
 })
@@ -40,7 +40,7 @@ class U500VC707DevKitConfig extends Config(
   new WithNExtTopInterrupts(0)   ++
   new U500VC707DevKitPeripherals ++
   new FreedomUVC707Config().alter((site,here,up) => {
-    case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
+    case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
     case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
     case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
     case DTSTimebase => BigInt(1000000)

src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala

@@ -30,7 +30,8 @@ object PinGen {
 class U500VC707DevKitFPGAChip(implicit override val p: Parameters)
     extends VC707Shell
     with HasPCIe
-    with HasDDR3 {
+    with HasDDR3
+    with HasDebugJTAG {
 
   //-----------------------------------------------------------------------
   // DUT

src/main/scala/unleashed/u500vc707devkit/System.scala

@@ -4,7 +4,7 @@ package sifive.freedom.unleashed.u500vc707devkit
 import Chisel._
 
 import freechips.rocketchip.config._
-import freechips.rocketchip.coreplex._
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
@@ -21,7 +21,7 @@ import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
 // U500VC707DevKitSystem
 //-------------------------------------------------------------------------
 
-class U500VC707DevKitSystem(implicit p: Parameters) extends RocketCoreplex
+class U500VC707DevKitSystem(implicit p: Parameters) extends RocketSubsystem
     with HasPeripheryMaskROMSlave
     with HasPeripheryDebug
     with HasSystemErrorSlave
@@ -34,7 +34,7 @@ class U500VC707DevKitSystem(implicit p: Parameters) extends RocketCoreplex
 }
 
 class U500VC707DevKitSystemModule[+L <: U500VC707DevKitSystem](_outer: L)
-  extends RocketCoreplexModule(_outer)
+  extends RocketSubsystemModuleImp(_outer)
     with HasRTCModuleImp
     with HasPeripheryDebugModuleImp
     with HasPeripheryUARTModuleImp