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iofpga: add a vc707 chiplink slave target

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This commit is contained in:
Wesley W. Terpstra
2018-03-22 18:27:19 -07:00
parent ac070218d1
commit 41f29484fd
2 changed files with 255 additions and 0 deletions
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22
Makefile.u500vc707iofpga Normal file
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# See LICENSE for license details.
base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
BUILD_DIR := $(base_dir)/builds/u500vc707iofpga
FPGA_DIR := $(base_dir)/fpga-shells/xilinx
MODEL := IOFPGAChip
PROJECT := sifive.freedom.unleashed.vc707.iofpga
export CONFIG_PROJECT := sifive.freedom.unleashed.vc707.iofpga
export CONFIG := IOFPGAConfig
export BOARD := vc707
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
$(FPGA_DIR)/$(BOARD)/vsrc/vc707reset.v \
$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
include common.mk