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Initial commit.

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SiFive
2016-11-29 05:23:11 -08:00
commit 3cf8128a30
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23
fpga/u500vc707devkit/Makefile Normal file
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VIVADO ?= vivado
VIVADOFLAGS := \
-nojournal -mode batch \
-source script/board.tcl \
-source script/prologue.tcl
bit := obj/system.bit
$(bit): script/impl.tcl script/init.tcl
VSRC_TOP=$(VSRC_TOP) VSRC_CONSTS=$(VSRC_CONSTS) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
.PHONY: bit
bit: $(bit)
mcs := obj/system.mcs
$(mcs): $(bit)
$(VIVADO) $(VIVADOFLAGS) script/cfgmem.tcl -tclargs $@ $^
.PHONY: mcs
mcs: $(mcs)
.PHONY: clean
clean::
rm -rf -- .Xil .ip_user_files *.os obj src/generated usage_statistics_webtalk.xml usage_statistics_webtalk.html *.log

90
fpga/u500vc707devkit/constrs/vc707-master.xdc Normal file
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#---------------Physical Constraints-----------------
set_property BOARD_PIN {clk_p} [get_ports sys_diff_clock_clk_p]
set_property BOARD_PIN {clk_n} [get_ports sys_diff_clock_clk_n]
set_property BOARD_PIN {reset} [get_ports reset]
# The MIG has its own create_clock
#create_clock -name ddr_ref_clk -period 5.0 [get_ports sys_diff_clock_clk_p]
set_input_jitter [get_clocks -of_objects [get_ports sys_diff_clock_clk_p]] 0.5
set_property BOARD_PIN {leds_8bits_tri_o_0} [get_ports led[0]]
set_property BOARD_PIN {leds_8bits_tri_o_1} [get_ports led[1]]
set_property BOARD_PIN {leds_8bits_tri_o_2} [get_ports led[2]]
set_property BOARD_PIN {leds_8bits_tri_o_3} [get_ports led[3]]
set_property BOARD_PIN {leds_8bits_tri_o_4} [get_ports led[4]]
set_property BOARD_PIN {leds_8bits_tri_o_5} [get_ports led[5]]
set_property BOARD_PIN {leds_8bits_tri_o_6} [get_ports led[6]]
set_property BOARD_PIN {leds_8bits_tri_o_7} [get_ports led[7]]
set_property PACKAGE_PIN AU33 [get_ports uart_rx]
set_property IOSTANDARD LVCMOS18 [get_ports uart_rx]
set_property IOB TRUE [get_ports uart_rx]
set_property PACKAGE_PIN AT32 [get_ports uart_ctsn]
set_property IOSTANDARD LVCMOS18 [get_ports uart_ctsn]
set_property IOB TRUE [get_ports uart_ctsn]
set_property PACKAGE_PIN AU36 [get_ports uart_tx]
set_property IOSTANDARD LVCMOS18 [get_ports uart_tx]
set_property IOB TRUE [get_ports uart_tx]
set_property PACKAGE_PIN AR34 [get_ports uart_rtsn]
set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn]
set_property IOB TRUE [get_ports uart_rtsn]
set_property IOB TRUE [get_cells "top/uart0/txm/out_reg"]
set_property IOB TRUE [get_cells "uart_rx_sync_reg[0]"]
# PCI Express
#FMC 1 refclk
#set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports {pci_exp_refclk_rxp}]
set_property PACKAGE_PIN A10 [get_ports {pci_exp_refclk_rxp}]
set_property PACKAGE_PIN A9 [get_ports {pci_exp_refclk_rxn}]
create_clock -name pcie_ref_clk -period 10 [get_ports pci_exp_refclk_rxp]
set_input_jitter [get_clocks -of_objects [get_ports pci_exp_refclk_rxp]] 0.5
set_property PACKAGE_PIN H4 [get_ports {pci_exp_txp[0]}]
set_property PACKAGE_PIN H3 [get_ports {pci_exp_txn[0]}]
set_property PACKAGE_PIN G6 [get_ports {pci_exp_rxp[0]}]
set_property PACKAGE_PIN G5 [get_ports {pci_exp_rxn[0]}]
# JTAG
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
set_property -dict { PACKAGE_PIN R32 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TCK}]
set_property -dict { PACKAGE_PIN W36 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
set_property -dict { PACKAGE_PIN W37 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
set_property -dict { PACKAGE_PIN V40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}]
# SDIO
#set_property -dict { PACKAGE_PIN AR32 IOSTANDARD LVCMOS18 } [get_ports {sdio_sdwp}]
#set_property -dict { PACKAGE_PIN AP32 IOSTANDARD LVCMOS18 } [get_ports {sdio_sddet}]
set_property -dict { PACKAGE_PIN AN30 IOSTANDARD LVCMOS18 IOB TRUE } [get_ports {sdio_clk}]
set_property -dict { PACKAGE_PIN AP30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_cmd}]
set_property -dict { PACKAGE_PIN AR30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[0]}]
set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[1]}]
set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}]
set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/blk_lnk_up"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/blk_lnk_up_d"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_reqSM_cs*"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/pcie_bme"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/s_axi_arvalid"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/arready_int"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/en_barhit"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_reqSM_ns*"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/illegal_burst_int"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/read_req_sent"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/slot_request"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/open_slot"]
#set_property MARK_DEBUG TRUE [get_nets "ip_axi_pcie_x1/inst/comp_axi_pcie_mm_s/comp_slave_bridge/comp_axi_slave_read/s_axi_arvalid"]
#set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/BufferedBroadcastAcquireTracker_2/state*"]
#set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/BufferedBroadcastAcquireTracker_1_1/*acquire*"]
#set_property MARK_DEBUG TRUE [get_nets "top/uncore/outmemsys/L2BroadcastHub_1/io_*"]
set_clock_groups -asynchronous \
-group [list \
[get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]] \
-group [list \
[get_clocks -include_generated_clocks -of_objects [get_ports sys_diff_clock_clk_p]]]

5
fpga/u500vc707devkit/script/board.tcl Normal file
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# See LICENSE for license details.
set name {vc707}
set part_fpga {xc7vx485tffg1761-2}
set part_board {xilinx.com:vc707:part0:1.3}
set bootrom_inst {rom}

10
fpga/u500vc707devkit/script/cfgmem.tcl Normal file
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lassign $argv mcsfile bitfile datafile
set iface bpix16
set size 128
set bitaddr 0x3000000
write_cfgmem -format mcs -interface $iface -size $size \
-loadbit "up ${bitaddr} ${bitfile}" \
-loaddata [expr {$datafile ne "" ? "up 0x400000 ${datafile}" : ""}] \
-file $mcsfile -force

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fpga/u500vc707devkit/script/impl.tcl Normal file
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set_param {messaging.defaultLimit} 1000000
read_ip [glob -directory $ipdir [file join * {*.xci}]]
synth_design -top $top -flatten_hierarchy rebuilt
write_checkpoint -force [file join $wrkdir post_synth]
opt_design
write_checkpoint -force [file join $wrkdir post_opt]
place_design
write_checkpoint -force [file join $wrkdir post_place]
phys_opt_design
power_opt_design
route_design
write_checkpoint -force [file join $wrkdir post_route]
write_bitstream -force [file join $wrkdir "${top}.bit"]
write_sdf -force [file join $wrkdir "${top}.sdf"]
write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]
write_debug_probes -force [file join $wrkdir "${top}.ltx"]
# AR 63042 <http://www.xilinx.com/support/answers/63041.html>:
# Work around the write_mem_info command not supporting "processor-less"
# (non-Microblaze) designs.
set bram_inst [get_cells -hierarchical "bram"]
if {$bram_inst ne ""} {
source [file join $scriptdir "bram.tcl"]
write_mmi [file join $wrkdir "${top}.mmi"] $bram_inst
}
if {[info exists bootrom_inst]} {
puts "Generating bootrom.mmi ..."
set rom_inst [get_cells -hierarchical "${bootrom_inst}"]
if {$rom_inst ne ""} {
source [file join $scriptdir "bram.tcl"]
write_mmi [file join $wrkdir "bootrom.mmi"] $rom_inst
}
}
set rptdir [file join $wrkdir report]
file mkdir $rptdir
set rptutil [file join $rptdir utilization.txt]
report_datasheet -file [file join $rptdir datasheet.txt]
report_utilization -hierarchical -file $rptutil
report_clock_utilization -file $rptutil -append
report_ram_utilization -file $rptutil -append -detail
report_timing_summary -file [file join $rptdir timing.txt] -max_paths 10
report_high_fanout_nets -file [file join $rptdir fanout.txt] -timing -load_types -max_nets 25
report_drc -file [file join $rptdir drc.txt]
report_io -file [file join $rptdir io.txt]
report_clocks -file [file join $rptdir clocks.txt]

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fpga/u500vc707devkit/script/init.tcl Normal file
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proc recglob { basedir pattern } {
set dirlist [glob -nocomplain -directory $basedir -type d *]
set findlist [glob -nocomplain -directory $basedir $pattern]
foreach dir $dirlist {
set reclist [recglob $dir $pattern]
set findlist [concat $findlist $reclist]
}
return $findlist
}
proc findincludedir { basedir pattern } {
#find all subdirectories containing ".vh" files
set vhfiles [recglob $basedir $pattern]
set vhdirs {}
foreach match $vhfiles {
lappend vhdirs [file dir $match]
}
set uniquevhdirs [lsort -unique $vhdirs]
return $uniquevhdirs
}
file mkdir $ipdir
update_ip_catalog -rebuild
source [file join $scriptdir ip.tcl]
# AR 58526 <http://www.xilinx.com/support/answers/58526.html>
set_property GENERATE_SYNTH_CHECKPOINT {false} [get_files -all {*.xci}]
set obj [get_ips]
generate_target all $obj
export_ip_user_files -of_objects $obj -no_script -force
set obj [current_fileset]
# Xilinx bug workaround
# scrape IP tree for directories containing .vh files
# [get_property include_dirs] misses all IP core subdirectory includes if user has specified -dir flag in create_ip
set property_include_dirs [get_property include_dirs $obj]
set ip_include_dirs [concat $property_include_dirs [findincludedir $ipdir "*.vh"]]
set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.h"]]
set ip_include_dirs [concat $ip_include_dirs [findincludedir $srcdir "*.vh"]]

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fpga/u500vc707devkit/script/ip.tcl Normal file
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#MIG
create_ip -vendor xilinx.com -library ip -name mig_7series -module_name vc707mig -dir $ipdir -force
set migprj [file join [pwd] $scriptdir {mig.prj}]
set_property CONFIG.XML_INPUT_FILE $migprj [get_ips vc707mig]
puts "SCRIPTDIR $scriptdir"
#AXI_PCIE
create_ip -vendor xilinx.com -library ip -version 2.8 -name axi_pcie -module_name vc707axi_to_pcie_x1 -dir $ipdir -force
set_property -dict [list \
CONFIG.AXIBAR2PCIEBAR_0 {0x60000000} \
CONFIG.AXIBAR2PCIEBAR_1 {0x00000000} \
CONFIG.AXIBAR2PCIEBAR_2 {0x00000000} \
CONFIG.AXIBAR2PCIEBAR_3 {0x00000000} \
CONFIG.AXIBAR2PCIEBAR_4 {0x00000000} \
CONFIG.AXIBAR2PCIEBAR_5 {0x00000000} \
CONFIG.AXIBAR_0 {0x60000000} \
CONFIG.AXIBAR_1 {0xFFFFFFFF} \
CONFIG.AXIBAR_2 {0xFFFFFFFF} \
CONFIG.AXIBAR_3 {0xFFFFFFFF} \
CONFIG.AXIBAR_4 {0xFFFFFFFF} \
CONFIG.AXIBAR_5 {0xFFFFFFFF} \
CONFIG.AXIBAR_AS_0 {true} \
CONFIG.AXIBAR_AS_1 {false} \
CONFIG.AXIBAR_AS_2 {false} \
CONFIG.AXIBAR_AS_3 {false} \
CONFIG.AXIBAR_AS_4 {false} \
CONFIG.AXIBAR_AS_5 {false} \
CONFIG.AXIBAR_HIGHADDR_0 {0x7FFFFFFF} \
CONFIG.AXIBAR_HIGHADDR_1 {0x00000000} \
CONFIG.AXIBAR_HIGHADDR_2 {0x00000000} \
CONFIG.AXIBAR_HIGHADDR_3 {0x00000000} \
CONFIG.AXIBAR_HIGHADDR_4 {0x00000000} \
CONFIG.AXIBAR_HIGHADDR_5 {0x00000000} \
CONFIG.AXIBAR_NUM {1} \
CONFIG.BAR0_ENABLED {true} \
CONFIG.BAR0_SCALE {Gigabytes} \
CONFIG.BAR0_SIZE {4} \
CONFIG.BAR0_TYPE {Memory} \
CONFIG.BAR1_ENABLED {false} \
CONFIG.BAR1_SCALE {N/A} \
CONFIG.BAR1_SIZE {8} \
CONFIG.BAR1_TYPE {N/A} \
CONFIG.BAR2_ENABLED {false} \
CONFIG.BAR2_SCALE {N/A} \
CONFIG.BAR2_SIZE {8} \
CONFIG.BAR2_TYPE {N/A} \
CONFIG.BAR_64BIT {true} \
CONFIG.BASEADDR {0x50000000} \
CONFIG.BASE_CLASS_MENU {Bridge_device} \
CONFIG.CLASS_CODE {0x060400} \
CONFIG.COMP_TIMEOUT {50us} \
CONFIG.Component_Name {design_1_axi_pcie_1_0} \
CONFIG.DEVICE_ID {0x7111} \
CONFIG.ENABLE_CLASS_CODE {true} \
CONFIG.HIGHADDR {0x53FFFFFF} \
CONFIG.INCLUDE_BAROFFSET_REG {true} \
CONFIG.INCLUDE_RC {Root_Port_of_PCI_Express_Root_Complex} \
CONFIG.INTERRUPT_PIN {false} \
CONFIG.MAX_LINK_SPEED {2.5_GT/s} \
CONFIG.MSI_DECODE_ENABLED {true} \
CONFIG.M_AXI_ADDR_WIDTH {32} \
CONFIG.M_AXI_DATA_WIDTH {64} \
CONFIG.NO_OF_LANES {X1} \
CONFIG.NUM_MSI_REQ {0} \
CONFIG.PCIEBAR2AXIBAR_0_SEC {1} \
CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \
CONFIG.PCIEBAR2AXIBAR_1 {0xFFFFFFFF} \
CONFIG.PCIEBAR2AXIBAR_1_SEC {1} \
CONFIG.PCIEBAR2AXIBAR_2 {0xFFFFFFFF} \
CONFIG.PCIEBAR2AXIBAR_2_SEC {1} \
CONFIG.PCIE_BLK_LOCN {X1Y1} \
CONFIG.PCIE_USE_MODE {GES_and_Production} \
CONFIG.REF_CLK_FREQ {100_MHz} \
CONFIG.REV_ID {0x00} \
CONFIG.SLOT_CLOCK_CONFIG {true} \
CONFIG.SUBSYSTEM_ID {0x0007} \
CONFIG.SUBSYSTEM_VENDOR_ID {0x10EE} \
CONFIG.SUB_CLASS_INTERFACE_MENU {Host_bridge} \
CONFIG.S_AXI_ADDR_WIDTH {32} \
CONFIG.S_AXI_DATA_WIDTH {64} \
CONFIG.S_AXI_ID_WIDTH {4} \
CONFIG.S_AXI_SUPPORTS_NARROW_BURST {false} \
CONFIG.VENDOR_ID {0x10EE} \
CONFIG.XLNX_REF_BOARD {None} \
CONFIG.axi_aclk_loopback {false} \
CONFIG.en_ext_ch_gt_drp {false} \
CONFIG.en_ext_clk {false} \
CONFIG.en_ext_gt_common {false} \
CONFIG.en_ext_pipe_interface {false} \
CONFIG.en_transceiver_status_ports {false} \
CONFIG.no_slv_err {false} \
CONFIG.rp_bar_hide {true} \
CONFIG.shared_logic_in_core {false} ] [get_ips vc707axi_to_pcie_x1]

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fpga/u500vc707devkit/script/mig.prj Normal file
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<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>vc707mig</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>
<Version>3.0</Version>
<SystemClock>Differential</SystemClock>
<ReferenceClock>Use System Clock</ReferenceClock>
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>0</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
<TimePeriod>1250</TimePeriod>
<VccAuxIO>2.0V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>200</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>800</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>64</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>14</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A20" SLEW="FAST" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B21" SLEW="FAST" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B17" SLEW="FAST" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A15" SLEW="FAST" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A21" SLEW="FAST" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="B19" SLEW="FAST" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C20" SLEW="FAST" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A19" SLEW="FAST" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A17" SLEW="FAST" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A16" SLEW="FAST" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D20" SLEW="FAST" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C18" SLEW="FAST" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D17" SLEW="FAST" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C19" SLEW="FAST" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D21" SLEW="FAST" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C21" SLEW="FAST" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D18" SLEW="FAST" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K17" SLEW="FAST" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="G18" SLEW="FAST" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="H19" SLEW="FAST" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K19" SLEW="FAST" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="J17" SLEW="FAST" name="ddr3_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="M13" SLEW="FAST" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="K15" SLEW="FAST" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F12" SLEW="FAST" name="ddr3_dm[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="A14" SLEW="FAST" name="ddr3_dm[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C23" SLEW="FAST" name="ddr3_dm[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="D25" SLEW="FAST" name="ddr3_dm[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="C31" SLEW="FAST" name="ddr3_dm[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F31" SLEW="FAST" name="ddr3_dm[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="FAST" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="FAST" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="FAST" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="FAST" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="FAST" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="FAST" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="FAST" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="FAST" name="ddr3_dq[16]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="FAST" name="ddr3_dq[17]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="FAST" name="ddr3_dq[18]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="FAST" name="ddr3_dq[19]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="FAST" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="FAST" name="ddr3_dq[20]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="FAST" name="ddr3_dq[21]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="FAST" name="ddr3_dq[22]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="FAST" name="ddr3_dq[23]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="FAST" name="ddr3_dq[24]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="FAST" name="ddr3_dq[25]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="FAST" name="ddr3_dq[26]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="FAST" name="ddr3_dq[27]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="FAST" name="ddr3_dq[28]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="FAST" name="ddr3_dq[29]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="FAST" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="FAST" name="ddr3_dq[30]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="FAST" name="ddr3_dq[31]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="FAST" name="ddr3_dq[32]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="FAST" name="ddr3_dq[33]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="FAST" name="ddr3_dq[34]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="FAST" name="ddr3_dq[35]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="FAST" name="ddr3_dq[36]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="FAST" name="ddr3_dq[37]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="FAST" name="ddr3_dq[38]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="FAST" name="ddr3_dq[39]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="FAST" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="FAST" name="ddr3_dq[40]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="FAST" name="ddr3_dq[41]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="FAST" name="ddr3_dq[42]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="FAST" name="ddr3_dq[43]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="FAST" name="ddr3_dq[44]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="FAST" name="ddr3_dq[45]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="FAST" name="ddr3_dq[46]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="FAST" name="ddr3_dq[47]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="FAST" name="ddr3_dq[48]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="FAST" name="ddr3_dq[49]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="FAST" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="FAST" name="ddr3_dq[50]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="FAST" name="ddr3_dq[51]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="FAST" name="ddr3_dq[52]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="FAST" name="ddr3_dq[53]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="FAST" name="ddr3_dq[54]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="FAST" name="ddr3_dq[55]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="FAST" name="ddr3_dq[56]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="FAST" name="ddr3_dq[57]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="FAST" name="ddr3_dq[58]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="FAST" name="ddr3_dq[59]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="FAST" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="FAST" name="ddr3_dq[60]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="FAST" name="ddr3_dq[61]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="FAST" name="ddr3_dq[62]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="FAST" name="ddr3_dq[63]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="FAST" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="FAST" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="FAST" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="FAST" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="FAST" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="FAST" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="FAST" name="ddr3_dqs_n[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="FAST" name="ddr3_dqs_n[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="FAST" name="ddr3_dqs_n[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="FAST" name="ddr3_dqs_n[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="FAST" name="ddr3_dqs_n[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="FAST" name="ddr3_dqs_n[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="FAST" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="FAST" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="FAST" name="ddr3_dqs_p[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="FAST" name="ddr3_dqs_p[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="FAST" name="ddr3_dqs_p[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="FAST" name="ddr3_dqs_p[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="FAST" name="ddr3_dqs_p[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="FAST" name="ddr3_dqs_p[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="H20" SLEW="FAST" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="E20" SLEW="FAST" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="C29" SLEW="FAST" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="F20" SLEW="FAST" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Clock>
<Pin PADName="E19/E18(CC_P/N)" Bank="38" name="sys_clk_p/n" />
</System_Clock>
<System_Control>
<Pin PADName="AV40" Bank="15" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >11</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>

74
fpga/u500vc707devkit/script/prologue.tcl Normal file
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@ -0,0 +1,74 @@
set scriptdir [file dirname [info script]]
set commondir [file dirname $scriptdir]
set srcdir [file join $commondir src]
set constrsdir [file join $commondir constrs]
set wrkdir [file join [pwd] obj]
set ipdir [file join $wrkdir ip]
set top {system}
create_project -part $part_fpga -in_memory
set_property -dict [list \
BOARD_PART $part_board \
TARGET_LANGUAGE {Verilog} \
SIMULATOR_LANGUAGE {Mixed} \
TARGET_SIMULATOR {XSim} \
DEFAULT_LIB {xil_defaultlib} \
IP_REPO_PATHS $ipdir \
] [current_project]
proc recglob { basedir pattern } {
set dirlist [glob -nocomplain -directory $basedir -type d *]
set findlist [glob -nocomplain -directory $basedir $pattern]
foreach dir $dirlist {
set reclist [recglob $dir $pattern]
set findlist [concat $findlist $reclist]
}
return $findlist
}
if {[get_filesets -quiet sources_1] eq ""} {
create_fileset -srcset sources_1
}
set obj [current_fileset]
set srcmainverilogfiles [recglob $srcdir "*.v"]
add_files -norecurse -fileset $obj $srcmainverilogfiles
if {[info exists ::env(EXTRA_VSRCS)]} {
set extra_vsrcs [split $::env(EXTRA_VSRCS)]
foreach extra_vsrc $extra_vsrcs {
add_files -norecurse -fileset $obj $extra_vsrc
}
}
## TODO: These paths and files should come from the caller, not within this script.
#if {[file exists [file join $srcdir include verilog]]} {
# add_files -norecurse -fileset $obj [file join $srcdir include verilog DebugTransportModuleJtag.v]
# add_files -norecurse -fileset $obj [file join $srcdir include verilog AsyncResetReg.v]
#}
set vsrc_top $::env(VSRC_TOP)
set vsrc_consts $::env(VSRC_CONSTS)
set_property verilog_define [list \
"VSRC_CONSTS=${vsrc_consts}" \
"VSRC_TOP=${vsrc_top}" \
] $obj
add_files -norecurse -fileset $obj $vsrc_top
add_files -norecurse -fileset $obj $vsrc_consts
if {[get_filesets -quiet sim_1] eq ""} {
create_fileset -simset sim_1
}
set obj [current_fileset -simset]
add_files -norecurse -fileset $obj [glob -directory $srcdir {*.v}]
set_property TOP {tb} $obj
if {[get_filesets -quiet constrs_1] eq ""} {
create_fileset -constrset constrs_1
}
set obj [current_fileset -constrset]
add_files -norecurse -fileset $obj [glob -directory $constrsdir {*.xdc}]

59
fpga/u500vc707devkit/src/sdio.v Normal file
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@ -0,0 +1,59 @@
// See LICENSE for license details.
`timescale 1ns/1ps
`default_nettype none
module sdio_spi_bridge (
input wire clk,
input wire reset,
// SDIO
inout wire sd_cmd,
inout wire [3:0] sd_dat,
output wire sd_sck,
// QUAD SPI
input wire spi_sck,
input wire [3:0] spi_dq_o,
output wire [3:0] spi_dq_i,
output wire spi_cs
);
wire mosi, miso;
reg miso_sync [1:0];
assign mosi = spi_dq_o[0];
assign spi_dq_i = {2'b00, miso_sync[1], 1'b0};
assign sd_sck = spi_sck;
IOBUF buf_cmd (
.IO(sd_cmd),
.I(mosi),
.O(),
.T(1'b0)
);
IOBUF buf_dat0 (
.IO(sd_dat[0]),
.I(),
.O(miso),
.T(1'b1)
);
IOBUF buf_dat3 (
.IO(sd_dat[3]),
.I(spi_cs),
.O(),
.T(1'b0)
);
always @(posedge clk) begin
if (reset) begin
miso_sync[0] <= 1'b0;
miso_sync[1] <= 1'b0;
end else begin
miso_sync[0] <= miso;
miso_sync[1] <= miso_sync[0];
end
end
endmodule
`default_nettype wire

171
fpga/u500vc707devkit/src/system.v Normal file
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@ -0,0 +1,171 @@
// See LICENSE for license details.
`timescale 1ns/1ps
`default_nettype none
`define STRINGIFY(x) `"x`"
`include `STRINGIFY(`VSRC_CONSTS)
module system
(
//200Mhz differential sysclk
input wire sys_diff_clock_clk_n,
input wire sys_diff_clock_clk_p,
//active high reset
input wire reset,
// DDR3 SDRAM
output wire [13:0] ddr3_addr,
output wire [2:0] ddr3_ba,
output wire ddr3_cas_n,
output wire [0:0] ddr3_ck_n,
output wire [0:0] ddr3_ck_p,
output wire [0:0] ddr3_cke,
output wire [0:0] ddr3_cs_n,
output wire [7:0] ddr3_dm,
inout wire [63:0] ddr3_dq,
inout wire [7:0] ddr3_dqs_n,
inout wire [7:0] ddr3_dqs_p,
output wire [0:0] ddr3_odt,
output wire ddr3_ras_n,
output wire ddr3_reset_n,
output wire ddr3_we_n,
// LED
output wire [7:0] led,
//UART
output wire uart_tx,
input wire uart_rx,
output wire uart_rtsn,
input wire uart_ctsn,
//SDIO
output wire sdio_clk,
inout wire sdio_cmd,
inout wire [3:0] sdio_dat,
//JTAG
input wire jtag_TCK,
input wire jtag_TMS,
input wire jtag_TDI,
output wire jtag_TDO,
//PCIe
output wire [0:0] pci_exp_txp,
output wire [0:0] pci_exp_txn,
input wire [0:0] pci_exp_rxp,
input wire [0:0] pci_exp_rxn,
input wire pci_exp_refclk_rxp,
input wire pci_exp_refclk_rxn
);
reg [1:0] uart_rx_sync;
wire [3:0] sd_spi_dq_i;
wire [3:0] sd_spi_dq_o;
wire sd_spi_sck;
wire sd_spi_cs;
wire top_clock,top_reset;
U500VC707DevKitTop top
(
//UART
.io_uarts_0_rxd(uart_rx_sync[1]),
.io_uarts_0_txd(uart_tx),
//SPI
.io_spis_0_sck(sd_spi_sck),
.io_spis_0_dq_0_i(sd_spi_dq_i[0]),
.io_spis_0_dq_1_i(sd_spi_dq_i[1]),
.io_spis_0_dq_2_i(sd_spi_dq_i[2]),
.io_spis_0_dq_3_i(sd_spi_dq_i[3]),
.io_spis_0_dq_0_o(sd_spi_dq_o[0]),
.io_spis_0_dq_1_o(sd_spi_dq_o[1]),
.io_spis_0_dq_2_o(sd_spi_dq_o[2]),
.io_spis_0_dq_3_o(sd_spi_dq_o[3]),
.io_spis_0_dq_0_oe(),
.io_spis_0_dq_1_oe(),
.io_spis_0_dq_2_oe(),
.io_spis_0_dq_3_oe(),
.io_spis_0_cs_0(sd_spi_cs),
//GPIO
.io_gpio_pins_0_i_ival(1'b0),
.io_gpio_pins_1_i_ival(1'b0),
.io_gpio_pins_2_i_ival(1'b0),
.io_gpio_pins_3_i_ival(1'b0),
.io_gpio_pins_0_o_oval(led[0]),
.io_gpio_pins_1_o_oval(led[1]),
.io_gpio_pins_2_o_oval(led[2]),
.io_gpio_pins_3_o_oval(led[3]),
.io_gpio_pins_0_o_oe(),
.io_gpio_pins_1_o_oe(),
.io_gpio_pins_2_o_oe(),
.io_gpio_pins_3_o_oe(),
.io_gpio_pins_0_o_pue(),
.io_gpio_pins_1_o_pue(),
.io_gpio_pins_2_o_pue(),
.io_gpio_pins_3_o_pue(),
.io_gpio_pins_0_o_ds(),
.io_gpio_pins_1_o_ds(),
.io_gpio_pins_2_o_ds(),
.io_gpio_pins_3_o_ds(),
//JTAG
.io_jtag_TRST(1'b0),
.io_jtag_TCK(jtag_TCK),
.io_jtag_TMS(jtag_TMS),
.io_jtag_TDI(jtag_TDI),
.io_jtag_DRV_TDO(),
.io_jtag_TDO(jtag_TDO),
//MIG
.io_xilinxvc707mig__inout_ddr3_dq(ddr3_dq),
.io_xilinxvc707mig__inout_ddr3_dqs_n(ddr3_dqs_n),
.io_xilinxvc707mig__inout_ddr3_dqs_p(ddr3_dqs_p),
.io_xilinxvc707mig_ddr3_addr(ddr3_addr),
.io_xilinxvc707mig_ddr3_ba(ddr3_ba),
.io_xilinxvc707mig_ddr3_ras_n(ddr3_ras_n),
.io_xilinxvc707mig_ddr3_cas_n(ddr3_cas_n),
.io_xilinxvc707mig_ddr3_we_n(ddr3_we_n),
.io_xilinxvc707mig_ddr3_reset_n(ddr3_reset_n),
.io_xilinxvc707mig_ddr3_ck_p(ddr3_ck_p),
.io_xilinxvc707mig_ddr3_ck_n(ddr3_ck_n),
.io_xilinxvc707mig_ddr3_cke(ddr3_cke),
.io_xilinxvc707mig_ddr3_cs_n(ddr3_cs_n),
.io_xilinxvc707mig_ddr3_dm(ddr3_dm),
.io_xilinxvc707mig_ddr3_odt(ddr3_odt),
//PCIe
.io_xilinxvc707pcie_pci_exp_txp(pci_exp_txp),
.io_xilinxvc707pcie_pci_exp_txn(pci_exp_txn),
.io_xilinxvc707pcie_pci_exp_rxp(pci_exp_rxp),
.io_xilinxvc707pcie_pci_exp_rxn(pci_exp_rxn),
//Clock + Reset
.io_pcie_refclk_p(pci_exp_refclk_rxp),
.io_pcie_refclk_n(pci_exp_refclk_rxn),
.io_sys_clk_p(sys_diff_clock_clk_p),
.io_sys_clk_n(sys_diff_clock_clk_n),
.io_sys_reset(reset),
//Misc outputs for system.v
.io_core_clock(top_clock),
.io_core_reset(top_reset)
);
sdio_spi_bridge ip_sdio_spi
(
.clk(top_clock),
.reset(top_reset),
.sd_cmd(sdio_cmd),
.sd_dat(sdio_dat),
.sd_sck(sdio_clk),
.spi_sck(sd_spi_sck),
.spi_dq_o(sd_spi_dq_o),
.spi_dq_i(sd_spi_dq_i),
.spi_cs(sd_spi_cs)
);
//UART
assign uart_rtsn =1'b0;
always @(posedge top_clock) begin
if (top_reset) begin
uart_rx_sync <= 2'b11;
end else begin
uart_rx_sync[0] <= uart_rx;
uart_rx_sync[1] <= uart_rx_sync[0];
end
end
assign led[7:4] = 4'b0000;
endmodule
`default_nettype wire