172 lines
4.4 KiB
Verilog
172 lines
4.4 KiB
Verilog
// See LICENSE for license details.
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`timescale 1ns/1ps
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`default_nettype none
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`define STRINGIFY(x) `"x`"
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`include `STRINGIFY(`VSRC_CONSTS)
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module system
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(
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//200Mhz differential sysclk
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input wire sys_diff_clock_clk_n,
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input wire sys_diff_clock_clk_p,
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//active high reset
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input wire reset,
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// DDR3 SDRAM
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output wire [13:0] ddr3_addr,
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output wire [2:0] ddr3_ba,
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output wire ddr3_cas_n,
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output wire [0:0] ddr3_ck_n,
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output wire [0:0] ddr3_ck_p,
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output wire [0:0] ddr3_cke,
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output wire [0:0] ddr3_cs_n,
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output wire [7:0] ddr3_dm,
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inout wire [63:0] ddr3_dq,
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inout wire [7:0] ddr3_dqs_n,
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inout wire [7:0] ddr3_dqs_p,
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output wire [0:0] ddr3_odt,
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output wire ddr3_ras_n,
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output wire ddr3_reset_n,
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output wire ddr3_we_n,
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// LED
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output wire [7:0] led,
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//UART
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output wire uart_tx,
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input wire uart_rx,
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output wire uart_rtsn,
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input wire uart_ctsn,
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//SDIO
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output wire sdio_clk,
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inout wire sdio_cmd,
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inout wire [3:0] sdio_dat,
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//JTAG
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input wire jtag_TCK,
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input wire jtag_TMS,
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input wire jtag_TDI,
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output wire jtag_TDO,
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//PCIe
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output wire [0:0] pci_exp_txp,
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output wire [0:0] pci_exp_txn,
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input wire [0:0] pci_exp_rxp,
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input wire [0:0] pci_exp_rxn,
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input wire pci_exp_refclk_rxp,
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input wire pci_exp_refclk_rxn
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);
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reg [1:0] uart_rx_sync;
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wire [3:0] sd_spi_dq_i;
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wire [3:0] sd_spi_dq_o;
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wire sd_spi_sck;
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wire sd_spi_cs;
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wire top_clock,top_reset;
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U500VC707DevKitTop top
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(
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//UART
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.io_uarts_0_rxd(uart_rx_sync[1]),
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.io_uarts_0_txd(uart_tx),
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//SPI
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.io_spis_0_sck(sd_spi_sck),
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.io_spis_0_dq_0_i(sd_spi_dq_i[0]),
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.io_spis_0_dq_1_i(sd_spi_dq_i[1]),
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.io_spis_0_dq_2_i(sd_spi_dq_i[2]),
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.io_spis_0_dq_3_i(sd_spi_dq_i[3]),
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.io_spis_0_dq_0_o(sd_spi_dq_o[0]),
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.io_spis_0_dq_1_o(sd_spi_dq_o[1]),
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.io_spis_0_dq_2_o(sd_spi_dq_o[2]),
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.io_spis_0_dq_3_o(sd_spi_dq_o[3]),
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.io_spis_0_dq_0_oe(),
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.io_spis_0_dq_1_oe(),
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.io_spis_0_dq_2_oe(),
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.io_spis_0_dq_3_oe(),
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.io_spis_0_cs_0(sd_spi_cs),
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//GPIO
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.io_gpio_pins_0_i_ival(1'b0),
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.io_gpio_pins_1_i_ival(1'b0),
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.io_gpio_pins_2_i_ival(1'b0),
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.io_gpio_pins_3_i_ival(1'b0),
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.io_gpio_pins_0_o_oval(led[0]),
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.io_gpio_pins_1_o_oval(led[1]),
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.io_gpio_pins_2_o_oval(led[2]),
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.io_gpio_pins_3_o_oval(led[3]),
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.io_gpio_pins_0_o_oe(),
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.io_gpio_pins_1_o_oe(),
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.io_gpio_pins_2_o_oe(),
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.io_gpio_pins_3_o_oe(),
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.io_gpio_pins_0_o_pue(),
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.io_gpio_pins_1_o_pue(),
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.io_gpio_pins_2_o_pue(),
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.io_gpio_pins_3_o_pue(),
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.io_gpio_pins_0_o_ds(),
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.io_gpio_pins_1_o_ds(),
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.io_gpio_pins_2_o_ds(),
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.io_gpio_pins_3_o_ds(),
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//JTAG
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.io_jtag_TRST(1'b0),
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.io_jtag_TCK(jtag_TCK),
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.io_jtag_TMS(jtag_TMS),
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.io_jtag_TDI(jtag_TDI),
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.io_jtag_DRV_TDO(),
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.io_jtag_TDO(jtag_TDO),
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//MIG
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.io_xilinxvc707mig__inout_ddr3_dq(ddr3_dq),
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.io_xilinxvc707mig__inout_ddr3_dqs_n(ddr3_dqs_n),
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.io_xilinxvc707mig__inout_ddr3_dqs_p(ddr3_dqs_p),
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.io_xilinxvc707mig_ddr3_addr(ddr3_addr),
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.io_xilinxvc707mig_ddr3_ba(ddr3_ba),
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.io_xilinxvc707mig_ddr3_ras_n(ddr3_ras_n),
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.io_xilinxvc707mig_ddr3_cas_n(ddr3_cas_n),
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.io_xilinxvc707mig_ddr3_we_n(ddr3_we_n),
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.io_xilinxvc707mig_ddr3_reset_n(ddr3_reset_n),
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.io_xilinxvc707mig_ddr3_ck_p(ddr3_ck_p),
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.io_xilinxvc707mig_ddr3_ck_n(ddr3_ck_n),
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.io_xilinxvc707mig_ddr3_cke(ddr3_cke),
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.io_xilinxvc707mig_ddr3_cs_n(ddr3_cs_n),
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.io_xilinxvc707mig_ddr3_dm(ddr3_dm),
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.io_xilinxvc707mig_ddr3_odt(ddr3_odt),
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//PCIe
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.io_xilinxvc707pcie_pci_exp_txp(pci_exp_txp),
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.io_xilinxvc707pcie_pci_exp_txn(pci_exp_txn),
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.io_xilinxvc707pcie_pci_exp_rxp(pci_exp_rxp),
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.io_xilinxvc707pcie_pci_exp_rxn(pci_exp_rxn),
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//Clock + Reset
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.io_pcie_refclk_p(pci_exp_refclk_rxp),
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.io_pcie_refclk_n(pci_exp_refclk_rxn),
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.io_sys_clk_p(sys_diff_clock_clk_p),
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.io_sys_clk_n(sys_diff_clock_clk_n),
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.io_sys_reset(reset),
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//Misc outputs for system.v
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.io_core_clock(top_clock),
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.io_core_reset(top_reset)
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);
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sdio_spi_bridge ip_sdio_spi
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(
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.clk(top_clock),
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.reset(top_reset),
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.sd_cmd(sdio_cmd),
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.sd_dat(sdio_dat),
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.sd_sck(sdio_clk),
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.spi_sck(sd_spi_sck),
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.spi_dq_o(sd_spi_dq_o),
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.spi_dq_i(sd_spi_dq_i),
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.spi_cs(sd_spi_cs)
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);
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//UART
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assign uart_rtsn =1'b0;
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always @(posedge top_clock) begin
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if (top_reset) begin
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uart_rx_sync <= 2'b11;
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end else begin
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uart_rx_sync[0] <= uart_rx;
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uart_rx_sync[1] <= uart_rx_sync[0];
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end
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end
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assign led[7:4] = 4'b0000;
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endmodule
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`default_nettype wire
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