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Switch to new XilinxML507MIG and connect top level signals

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This commit is contained in:
Klemens Schölhorn
2018-05-10 00:37:00 +02:00
parent 7b46ed6b7c
commit 291a765b8d
4 changed files with 7 additions and 5 deletions
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5
src/main/scala/unleashed/u500ml507devkit/System.scala
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@ -15,7 +15,7 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.terminal._
import sifive.freedom.unleashed.u500ml507devkit.fpga._
import sifive.fpgashells.devices.xilinx.xilinxml507mig._
//-------------------------------------------------------------------------
// U500ML507DevKitSystem
@ -40,7 +40,8 @@ class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
with HasPeripheryUARTModuleImp
with HasPeripheryTerminalModuleImp
with HasPeripherySPIModuleImp
with HasPeripheryGPIOModuleImp {
with HasPeripheryGPIOModuleImp
with HasMemoryML507ModuleImp {
// Reset vector is set to the location of the mask rom
val maskROMParams = p(PeripheryMaskROMKey)
global_reset_vector := maskROMParams(0).address.U