Remove vc707 memory interface from ml507

src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala

@@ -29,7 +29,6 @@ object PinGen {
 
 class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
     extends VC707Shell
-    with HasDDR3
     with HasDebugJTAG {
 
   //-----------------------------------------------------------------------
@@ -48,7 +47,6 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
     connectDebugJTAG(dut)
     connectSPI      (dut)
     connectUART     (dut)
-    connectMIG      (dut)
 
     //---------------------------------------------------------------------
     // GPIO

src/main/scala/unleashed/u500ml507devkit/System.scala

@@ -14,9 +14,6 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 
-import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
-import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
-
 //-------------------------------------------------------------------------
 // U500ML507DevKitSystem
 //-------------------------------------------------------------------------
@@ -27,8 +24,7 @@ class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem
     with HasSystemErrorSlave
     with HasPeripheryUART
     with HasPeripherySPI
-    with HasPeripheryGPIO
-    with HasMemoryXilinxVC707MIG {
+    with HasPeripheryGPIO {
   override lazy val module = new U500ML507DevKitSystemModule(this)
 }
 
@@ -38,8 +34,7 @@ class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
     with HasPeripheryDebugModuleImp
     with HasPeripheryUARTModuleImp
     with HasPeripherySPIModuleImp
-    with HasPeripheryGPIOModuleImp
-    with HasMemoryXilinxVC707MIGModuleImp {
+    with HasPeripheryGPIOModuleImp {
   // Reset vector is set to the location of the mask rom
   val maskROMParams = p(PeripheryMaskROMKey)
   global_reset_vector := maskROMParams(0).address.U