Remove vc707 memory interface from ml507
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@ -14,9 +14,6 @@ import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
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import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
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//-------------------------------------------------------------------------
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// U500ML507DevKitSystem
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//-------------------------------------------------------------------------
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@ -27,8 +24,7 @@ class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem
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with HasSystemErrorSlave
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with HasPeripheryUART
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with HasPeripherySPI
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with HasPeripheryGPIO
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with HasMemoryXilinxVC707MIG {
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with HasPeripheryGPIO {
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override lazy val module = new U500ML507DevKitSystemModule(this)
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}
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@ -38,8 +34,7 @@ class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
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with HasPeripheryDebugModuleImp
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with HasPeripheryUARTModuleImp
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with HasPeripherySPIModuleImp
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with HasPeripheryGPIOModuleImp
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with HasMemoryXilinxVC707MIGModuleImp {
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with HasPeripheryGPIOModuleImp {
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// Reset vector is set to the location of the mask rom
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val maskROMParams = p(PeripheryMaskROMKey)
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global_reset_vector := maskROMParams(0).address.U
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