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fpga-shells/xilinx/common/vsrc/PowerOnResetFPGAOnly.v
2017-08-16 11:23:45 -07:00

16 lines
248 B
Verilog

// See LICENSE file for license details.
module PowerOnResetFPGAOnly(
input clock,
output reg power_on_reset
);
initial begin
power_on_reset <= 1'b1;
end
always @(posedge clock) begin
power_on_reset <= 1'b0;
end
endmodule