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fpga-shells/xilinx/common/tcl/bitstream.tcl
2017-08-16 11:23:45 -07:00

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365 B
Tcl

# See LICENSE for license details.
# Write a bitstream for the current design
write_bitstream -force [file join $wrkdir "${top}.bit"]
# Save the timing delays for cells in the design in SDF format
write_sdf -force [file join $wrkdir "${top}.sdf"]
# Export the current netlist in verilog format
write_verilog -mode timesim -force [file join ${wrkdir} "${top}.v"]