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base: riscv:b49f5cfa78df56a58a6b07c5b8d1588d950dcc68
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riscv:master
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compare: riscv:12cb1c2fa553a68a0ef7b584a35416f695996575
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riscv:ml507
riscv:master

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src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala
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@ -44,10 +44,7 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
// Corresponds to MIG interface with 64 bit width and a burst length of 4 // Corresponds to MIG interface with 64 bit width and a burst length of 4
val width = 256 val width = 256
val beatBytes = width/8 // 32 byte (half a cache-line, fragmented) val beatBytes = width/8 // 32 byte (half a cache-line, fragmented)
val crossing = AsynchronousCrossing(8)
val address_range = AddressRange.fromSets(c.address).head
require(log2Ceil(address_range.size) == 28, "Max 256MiB DIMMs supported")
val crossing = AsynchronousCrossing(1)
val device = new MemoryDevice val device = new MemoryDevice
val node = TLManagerNode( val node = TLManagerNode(
@ -93,18 +90,13 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
// with respect to the size and address. So we can directly forward // with respect to the size and address. So we can directly forward
// the mask, (relative) address and data to the MIG interface. // the mask, (relative) address and data to the MIG interface.
// An AddressSet is always aligned, so we don't need to subtract the
// base address, we can just take the lower bits. The lowest 5 bits
// are used for indexing the 32 byte word of the MIG.
val address = in.a.bits.address(27, 0) & "hFFFFFE0".U
// Save the source, size and type of the requests in a queue so we // Save the source, size and type of the requests in a queue so we
// can synthesize the right responses in fifo order. The length also // can synthesize the right responses in fifo order. The length also
// determines the maximum number of in-flight requests. // determines the maximum number of in-flight requests.
val ack_queue = Module(new Queue(new ResponseQueueIO, 2)) val ack_queue = Module(new Queue(new ResponseQueueIO, 4))
// Pass data directly to the controller // Pass data directly to the controller
controller.io.request_addr := address controller.io.request_addr := in.a.bits.address(27, 0) & "hFFFFFE0".U
controller.io.request_type := !edge.hasData(in.a.bits) controller.io.request_type := !edge.hasData(in.a.bits)
controller.io.request_data := in.a.bits.data controller.io.request_data := in.a.bits.data
// TL uses high to indicate valid data while mig uses low // TL uses high to indicate valid data while mig uses low
@ -127,7 +119,7 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
// avoid losing any responses, this queue *must* be at least as wide // avoid losing any responses, this queue *must* be at least as wide
// as the ack queue, so that we can catch all responses, even if the // as the ack queue, so that we can catch all responses, even if the
// ack queue is completely filled with read requests. // ack queue is completely filled with read requests.
val response_queue = Module(new Queue(controller.io.response_data, 2)) val response_queue = Module(new Queue(controller.io.response_data, 4))
response_queue.io.enq.bits := controller.io.response_data response_queue.io.enq.bits := controller.io.response_data
response_queue.io.enq.valid := controller.io.response_valid response_queue.io.enq.valid := controller.io.response_valid