riscv/fpga-shells
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base: riscv:2ff28e6af695cecfa089da1ee26288517656c81d
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riscv:ml507
riscv:master
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compare: riscv:e9625bf8ee21c467a8bb6df3f9304c17411c93b6
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riscv:ml507
riscv:master

No commits in common. "2ff28e6af695cecfa089da1ee26288517656c81d" and "e9625bf8ee21c467a8bb6df3f9304c17411c93b6" have entirely different histories.
2ff28e6af6 ... e9625bf8ee

1 changed files with 4 additions and 4 deletions
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src/main/scala/shell/xilinx/ML507Shell.scala
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@ -98,7 +98,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// active high reset
val reset = IO(Input(Bool()))
val reset_led = IO(Output(Bool()))
// LED
val led = IO(Vec(8, Output(Bool())))
@ -106,6 +105,8 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// UART
val uart_tx = IO(Output(Bool()))
val uart_rx = IO(Input(Bool()))
val uart_rtsn = IO(Output(Bool()))
val uart_ctsn = IO(Input(Bool()))
// SDIO
val sdio_clk = IO(Output(Bool()))
@ -175,9 +176,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// Allow the debug module to reset everything. Resets the MIG
sys_reset := reset | dut_ndreset
// Status LED for reset
reset_led := reset
//-----------------------------------------------------------------------
// Clock Generator
//-----------------------------------------------------------------------
@ -227,6 +225,8 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// UART
//-----------------------------------------------------------------------
uart_rtsn := false.B
def connectUART(dut: HasPeripheryUARTModuleImp): Unit = {
val uartParams = p(PeripheryUARTKey)
if (!uartParams.isEmpty) {