signal_bundles: Use the new way as .fromPorts is gone
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@ -166,7 +166,7 @@ abstract class ArtyShell(implicit val p: Parameters) extends RawModule {
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val qspi_params = qspiParams(0)
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val qspi_pins = Wire(new SPIPins(() => {new BasePin()}, qspi_params))
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qspi_pins.fromPort(
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SPIPinsFromPort(qspi_pins,
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dut.qspi(0),
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dut.clock,
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dut.reset,
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