riscv/fpga-shells
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signal_bundles: Use the new way as .fromPorts is gone

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Megan Wachs 2017-09-22 13:31:11 -07:00
parent e9019d7570
commit bf48e2c7c4
1 changed files with 1 additions and 1 deletions
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src/main/scala/shell/xilinx/ArtyShell.scala
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@ -166,7 +166,7 @@ abstract class ArtyShell(implicit val p: Parameters) extends RawModule {
val qspi_params = qspiParams(0) val qspi_params = qspiParams(0)
val qspi_pins = Wire(new SPIPins(() => {new BasePin()}, qspi_params)) val qspi_pins = Wire(new SPIPins(() => {new BasePin()}, qspi_params))
qspi_pins.fromPort( SPIPinsFromPort(qspi_pins,
dut.qspi(0), dut.qspi(0),
dut.clock, dut.clock,
dut.reset, dut.reset,