riscv/fpga-shells
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Pass debug hooks through project-specific makefiles

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This commit is contained in:
Shreesha Srinath
2017-08-18 11:27:02 -07:00
parent c58e79f155
commit ae767458af
3 changed files with 6 additions and 8 deletions
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3
xilinx/common/tcl/post-impl-debug.tcl
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@@ -1,3 +0,0 @@
# See LICENSE for license details.
# Write debug probes, save MMI for BRAMs in the design

3
xilinx/common/tcl/pre-impl-debug.tcl
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@@ -1,3 +0,0 @@
# See LICENSE for license details.
# Instantiate ILAs

8
xilinx/common/tcl/vivado.tcl
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@@ -4,7 +4,9 @@
source [file join $scriptdir "synth.tcl"] source [file join $scriptdir "synth.tcl"]
# Pre-implementation debug # Pre-implementation debug
source [file join $scriptdir "pre-impl-debug.tcl"] if {[info exists ::env(PRE_IMPL_DEBUG_TCL)]} {
source [file join $scriptdir ::env(PRE_IMPL_DEBUG_TCL)]
}
# Post synthesis optimization # Post synthesis optimization
source [file join $scriptdir "opt.tcl"] source [file join $scriptdir "opt.tcl"]
@@ -19,7 +21,9 @@ source [file join $scriptdir "route.tcl"]
source [file join $scriptdir "bitstream.tcl"] source [file join $scriptdir "bitstream.tcl"]
# Post-implementation debug # Post-implementation debug
source [file join $scriptdir "post-impl-debug.tcl"] if {[info exists ::env(POST_IMPL_DEBUG_TCL)]} {
source [file join $scriptdir ::env(POST_IMPL_DEBUG_TCL)]
}
# Create reports for the current implementation # Create reports for the current implementation
source [file join $scriptdir "report.tcl"] source [file join $scriptdir "report.tcl"]