xilinxVC707mig: convert to the island pattern (#12)
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@ -8,6 +8,7 @@ import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import sifive.fpgashells.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
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case class XilinxVC707MIGParams(
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@ -22,15 +23,16 @@ class XilinxVC707MIGPads(depth : BigInt) extends VC707MIGIODDR(depth) {
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class XilinxVC707MIGIO(depth : BigInt) extends VC707MIGIODDR(depth) with VC707MIGIOClocksReset
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class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
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class XilinxVC707MIGIsland(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule with HasCrossing {
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val ranges = AddressRange.fromSets(c.address)
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require (ranges.size == 1, "DDR range must be contiguous")
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val offset = ranges.head.base
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val depth = ranges.head.size
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val crossing = AsynchronousCrossing(8)
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require((depth<=0x100000000L),"vc707mig supports upto 4GB depth configuraton")
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val device = new MemoryDevice
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val axi4 = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
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val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = c.address,
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resources = device.reg,
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@ -40,21 +42,6 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
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supportsRead = TransferSizes(1, 256*8))),
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beatBytes = 8)))
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val xing = LazyModule(new TLAsyncCrossing)
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val toaxi4 = LazyModule(new TLToAXI4(adapterName = Some("mem"), stripBits = 1))
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val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
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val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
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val yank = LazyModule(new AXI4UserYanker)
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val buffer = LazyModule(new AXI4Buffer)
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val node: TLInwardNode = xing.node
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toaxi4.node := xing.node
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axi4 := buffer.node
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buffer.node := yank.node
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yank.node := deint.node
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deint.node := indexer.node
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indexer.node := toaxi4.node
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val port = new XilinxVC707MIGIO(depth)
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@ -62,6 +49,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
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//MIG black box instantiation
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val blackbox = Module(new vc707mig(depth))
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val (axi_async, _) = node.in(0)
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//pins to top level
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@ -88,17 +76,6 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
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//NO_BUFFER clock
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blackbox.io.sys_clk_i := io.port.sys_clk_i
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//user interface signals
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val (axi_async, _) = axi4.in(0)
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xing.module.io.in_clock := clock
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xing.module.io.in_reset := reset
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xing.module.io.out_clock := blackbox.io.ui_clk
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xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
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Seq(toaxi4, indexer, deint, yank, buffer) foreach { lm =>
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lm.module.clock := blackbox.io.ui_clk
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lm.module.reset := blackbox.io.ui_clk_sync_rst
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}
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io.port.ui_clk := blackbox.io.ui_clk
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io.port.ui_clk_sync_rst := blackbox.io.ui_clk_sync_rst
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io.port.mmcm_locked := blackbox.io.mmcm_locked
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@ -166,3 +143,30 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
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//mig.device_temp :- unconnceted
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}
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}
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class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
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val ranges = AddressRange.fromSets(c.address)
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val depth = ranges.head.size
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val buffer = LazyModule(new TLBuffer)
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val toaxi4 = LazyModule(new TLToAXI4(adapterName = Some("mem"), stripBits = 1))
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val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
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val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
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val yank = LazyModule(new AXI4UserYanker)
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val island = LazyModule(new XilinxVC707MIGIsland(c))
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val node: TLInwardNode =
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island.node := island.crossAXI4In := yank.node := deint.node := indexer.node := toaxi4.node := buffer.node
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val port = new XilinxVC707MIGIO(depth)
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})
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io.port <> island.module.io.port
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// Shove the island
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island.module.clock := io.port.ui_clk
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island.module.reset := io.port.ui_clk_sync_rst
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}
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}
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@ -7,6 +7,7 @@ import freechips.rocketchip.coreplex.CacheBlockBytes
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
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import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
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@ -5,7 +5,7 @@ import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple}
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util.{ElaborationArtefacts}
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// IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0
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