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xilinxVC707mig: convert to the island pattern (#12)

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This commit is contained in:
Wesley W. Terpstra
2017-10-26 16:38:52 -07:00
committed by GitHub
parent eaf1c3ed54
commit 65ac5d4588
3 changed files with 34 additions and 29 deletions
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src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
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@@ -5,7 +5,7 @@ import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple}
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util.{ElaborationArtefacts}
// IP VLNV: xilinx.com:customize_ip:vc707pcietoaxi:1.0