79 lines
2.1 KiB
Coq
79 lines
2.1 KiB
Coq
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// See LICENSE for license details.
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`timescale 1ns/1ps
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`default_nettype none
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`define RESET_SYNC 4
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`define DEBOUNCE_BITS 8
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module vc707reset(
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// Asynchronous reset input, should be held high until
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// all clocks are locked and power is stable.
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input wire areset,
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// Clock domains are brought up in increasing order
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// All clocks are reset for at least 2^DEBOUNCE_BITS * period(clock1)
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input wire clock1,
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output wire reset1,
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input wire clock2,
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output wire reset2,
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input wire clock3,
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output wire reset3,
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input wire clock4,
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output wire reset4
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);
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sifive_reset_hold hold_clock0(areset, clock1, reset1);
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sifive_reset_sync sync_clock2(reset1, clock2, reset2);
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sifive_reset_sync sync_clock3(reset2, clock3, reset3);
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sifive_reset_sync sync_clock4(reset3, clock4, reset4);
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endmodule
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// Assumes that areset is held for more than one clock
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// Allows areset to be deasserted asynchronously
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module sifive_reset_sync(
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input wire areset,
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input wire clock,
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output wire reset
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);
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reg [`RESET_SYNC-1:0] gen_reset = {`RESET_SYNC{1'b1}};
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always @(posedge clock, posedge areset) begin
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if (areset) begin
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gen_reset <= {`RESET_SYNC{1'b1}};
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end else begin
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gen_reset <= {1'b0,gen_reset[`RESET_SYNC-1:1]};
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end
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end
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assign reset = gen_reset[0];
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endmodule
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module sifive_reset_hold(
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input wire areset,
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input wire clock,
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output wire reset
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);
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wire raw_reset;
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reg [`RESET_SYNC-1:0] sync_reset = {`RESET_SYNC{1'b1}};
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reg [`DEBOUNCE_BITS:0] debounce_reset = {`DEBOUNCE_BITS{1'b1}};
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wire out_reset;
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// Captures reset even if clock is not running
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sifive_reset_sync capture(areset, clock, raw_reset);
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// Remove any glitches due to runt areset
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always @(posedge clock) begin
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sync_reset <= {raw_reset,sync_reset[`RESET_SYNC-1:1]};
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end
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// Debounce the reset
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assign out_reset = debounce_reset[`DEBOUNCE_BITS];
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always @(posedge clock) begin
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if (sync_reset[0]) begin
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debounce_reset <= {(`DEBOUNCE_BITS+1){1'b1}};
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end else begin
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debounce_reset <= debounce_reset - out_reset;
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end
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end
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assign reset = out_reset;
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endmodule
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`default_nettype wire
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