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fpga-shells/xilinx/common/tcl/vivado.tcl

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# See LICENSE for license details.
# Synthesize the design
source [file join $scriptdir "synth.tcl"]
# Pre-implementation debug
if {[info exists ::env(PRE_IMPL_DEBUG_TCL)]} {
source [file join $scriptdir ::env(PRE_IMPL_DEBUG_TCL)]
}
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# Post synthesis optimization
source [file join $scriptdir "opt.tcl"]
# Place the design
source [file join $scriptdir "place.tcl"]
# Route the design
source [file join $scriptdir "route.tcl"]
# Generate bitstream and save verilog netlist
source [file join $scriptdir "bitstream.tcl"]
# Post-implementation debug
if {[info exists ::env(POST_IMPL_DEBUG_TCL)]} {
source [file join $scriptdir ::env(POST_IMPL_DEBUG_TCL)]
}
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# Create reports for the current implementation
source [file join $scriptdir "report.tcl"]