2017-08-16 20:23:45 +02:00
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# See LICENSE for license details.
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# Synthesize the design
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source [file join $scriptdir "synth.tcl"]
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# Pre-implementation debug
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2017-08-18 20:27:02 +02:00
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if {[info exists ::env(PRE_IMPL_DEBUG_TCL)]} {
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source [file join $scriptdir ::env(PRE_IMPL_DEBUG_TCL)]
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}
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2017-08-16 20:23:45 +02:00
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# Post synthesis optimization
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source [file join $scriptdir "opt.tcl"]
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# Place the design
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source [file join $scriptdir "place.tcl"]
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# Route the design
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source [file join $scriptdir "route.tcl"]
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# Generate bitstream and save verilog netlist
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source [file join $scriptdir "bitstream.tcl"]
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# Post-implementation debug
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2017-08-18 20:27:02 +02:00
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if {[info exists ::env(POST_IMPL_DEBUG_TCL)]} {
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source [file join $scriptdir ::env(POST_IMPL_DEBUG_TCL)]
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}
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2017-08-16 20:23:45 +02:00
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# Create reports for the current implementation
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source [file join $scriptdir "report.tcl"]
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