1
0
Fork 0
fpga-shells/xilinx/common/tcl/place.tcl

14 lines
331 B
Tcl
Raw Normal View History

2017-08-16 20:23:45 +02:00
# See LICENSE for license details.
# Place the current design
place_design -directive Explore
# Optimize the current placed netlist
phys_opt_design -directive Explore
# Optimize dynamic power using intelligent clock gating
power_opt_design
# Checkpoint the current design
write_checkpoint -force [file join $wrkdir post_place]