60 lines
1004 B
Coq
60 lines
1004 B
Coq
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// See LICENSE for license details.
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`timescale 1ns/1ps
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`default_nettype none
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module sdio_spi_bridge (
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input wire clk,
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input wire reset,
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// SDIO
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inout wire sd_cmd,
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inout wire [3:0] sd_dat,
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output wire sd_sck,
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// QUAD SPI
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input wire spi_sck,
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input wire [3:0] spi_dq_o,
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output wire [3:0] spi_dq_i,
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output wire spi_cs
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);
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wire mosi, miso;
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reg miso_sync [1:0];
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assign mosi = spi_dq_o[0];
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assign spi_dq_i = {2'b00, miso_sync[1], 1'b0};
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assign sd_sck = spi_sck;
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IOBUF buf_cmd (
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.IO(sd_cmd),
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.I(mosi),
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.O(),
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.T(1'b0)
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);
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IOBUF buf_dat0 (
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.IO(sd_dat[0]),
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.I(),
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.O(miso),
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.T(1'b1)
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);
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IOBUF buf_dat3 (
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.IO(sd_dat[3]),
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.I(spi_cs),
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.O(),
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.T(1'b0)
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);
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always @(posedge clk) begin
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if (reset) begin
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miso_sync[0] <= 1'b0;
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miso_sync[1] <= 1'b0;
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end else begin
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miso_sync[0] <= miso;
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miso_sync[1] <= miso_sync[0];
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end
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end
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endmodule
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`default_nettype wire
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