123 lines
4.4 KiB
C
123 lines
4.4 KiB
C
#ifndef _AVR_MACROS_H_
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#define _AVR_MACROS_H_
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//// Compare Output Mode for Channel A
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#define TCCRnA_COMnA_disconnected 0x00
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#define TCCRnA_COMnA_toggle 0x40
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#define TCCRnA_COMnA_low 0x80
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#define TCCRnA_COMnA_high 0xf0
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#define TCCRnA_COMnA_CLEAR ~ ( TCCRnA_COMnA_disconnected \
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| TCCRnA_COMnA_toggle \
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| TCCRnA_COMnA_low \
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| TCCRnA_COMnA_high )
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// Compare Output Mode for Channel B
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#define TCCRnA_COMnB_disconnected 0x00
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#define TCCRnA_COMnB_toggle 0x10
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#define TCCRnA_COMnB_low 0x20
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#define TCCRnA_COMnB_high 0x30
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#define TCCRnA_COMnB_CLEAR ~ ( TCCRnA_COMnB_disconnected \
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| TCCRnA_COMnB_toggle \
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| TCCRnA_COMnB_low \
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| TCCRnA_COMnB_high )
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// Timer/CounterN Interrupt Mask Register
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#define TIMSKn_ENABLE_INTERRUPT_on_nothing 0x00
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#define TIMSKn_ENABLE_INTERRUPT_on_overflow 0x01
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#define TIMSKn_ENABLE_INTERRUPT_on_compare_match_A 0x02
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#define TIMSKn_ENABLE_INTERRUPT_on_compare_match_B 0x04
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#define TIMSKn_ENABLE_INTERRUPT_CLEAR ~ ( TIMSKn_ENABLE_INTERRUPT_on_nothing \
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| TIMSKn_ENABLE_INTERRUPT_on_overflow \
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| TIMSKn_ENABLE_INTERRUPT_on_compare_match_A \
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| TIMSKn_ENABLE_INTERRUPT_on_compare_match_B )
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/**********************************************************/
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// Timer/Counter0 Control Register A
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// Compare Output Mode for Channel A
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#define TCCR0A_COM0A_disconnected 0x00
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#define TCCR0A_COM0A_toggle 0x40
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#define TCCR0A_COM0A_low 0x80
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#define TCCR0A_COM0A_high 0xf0
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// Compare Output Mode for Channel B
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#define TCCR0A_COM0B_disconnected 0x00
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#define TCCR0A_COM0B_toggle 0x10
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#define TCCR0A_COM0B_low 0x20
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#define TCCR0A_COM0B_high 0x30
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// Timer/Counter0 Control Register B
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// Clock Select 0 (prescaler)
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#define TCCR0B_CS0_stopped 0x00
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#define TCCR0B_CS0_prescale1 0x01
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#define TCCR0B_CS0_prescale8 0x02
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#define TCCR0B_CS0_prescale64 0x03
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#define TCCR0B_CS0_prescale256 0x04
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#define TCCR0B_CS0_prescale1024 0x05
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#define TCCR0B_CS0_falling_on_T0 0x06
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#define TCCR0B_CS0_rising_on_T0 0x07
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// Timer/Counter0 Interrupt Mask Register
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#define TIMSK0_ENABLE_INTERRUPT_on_nothing 0x00
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#define TIMSK0_ENABLE_INTERRUPT_on_overflow 0x01
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#define TIMSK0_ENABLE_INTERRUPT_on_compare_match_A 0x02
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#define TIMSK0_ENABLE_INTERRUPT_on_compare_match_B 0x04
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// Timer/Counter1 Control Register A
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// Compare Output Mode for Channel A
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#define TCCR1A_COM1A_disconnected 0x00
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#define TCCR1A_COM1A_toggle 0x40
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#define TCCR1A_COM1A_low 0x80
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#define TCCR1A_COM1A_high 0xf0
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// Compare Output Mode for Channel B
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#define TCCR1A_COM1B_disconnected 0x00
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#define TCCR1A_COM1B_toggle 0x10
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#define TCCR1A_COM1B_low 0x20
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#define TCCR1A_COM1B_high 0x30
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// Timer/Counter1 Control Register B
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// Clock Select 1 (prescaler)
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#define TCCR1B_CS1_stopped 0x00
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#define TCCR1B_CS1_prescale1 0x01
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#define TCCR1B_CS1_prescale8 0x02
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#define TCCR1B_CS1_prescale64 0x03
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#define TCCR1B_CS1_prescale256 0x04
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#define TCCR1B_CS1_prescale1024 0x05
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#define TCCR1B_CS1_falling_on_T1 0x06
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#define TCCR1B_CS1_rising_on_T1 0x07
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// Timer/Counter1 Interrupt Mask Register
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#define TIMSK1_ENABLE_INTERRUPT_on_nothing 0x00
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#define TIMSK1_ENABLE_INTERRUPT_on_overflow 0x01
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#define TIMSK1_ENABLE_INTERRUPT_on_compare_match_A 0x02
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#define TIMSK1_ENABLE_INTERRUPT_on_compare_match_B 0x04
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// Timer/Counter2 Control Register A
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// Compare Output Mode for Channel A
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#define TCCR2A_COM2A_disconnected 0x00
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#define TCCR2A_COM2A_toggle 0x40
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#define TCCR2A_COM2A_low 0x80
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#define TCCR2A_COM2A_high 0xf0
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// Compare Output Mode for Channel B
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#define TCCR2A_COM2B_disconnected 0x00
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#define TCCR2A_COM2B_toggle 0x10
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#define TCCR2A_COM2B_low 0x20
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#define TCCR2A_COM2B_high 0x30
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// Timer/Counter1 Control Register B
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// Clock Select 1 (prescaler)
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#define TCCR2B_CS2_stopped 0x00
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#define TCCR2B_CS2_prescale1 0x01
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#define TCCR2B_CS2_prescale8 0x02
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#define TCCR2B_CS2_prescale32 0x03
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#define TCCR2B_CS2_prescale64 0x04
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#define TCCR2B_CS2_prescale128 0x05
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#define TCCR2B_CS2_prescale256 0x06
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#define TCCR2B_CS2_prescale1024 0x07
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// Timer/Counter1 Interrupt Mask Register
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#define TIMSK2_ENABLE_INTERRUPT_on_nothing 0x00
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#define TIMSK2_ENABLE_INTERRUPT_on_overflow 0x01
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#define TIMSK2_ENABLE_INTERRUPT_on_compare_match_A 0x02
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#define TIMSK2_ENABLE_INTERRUPT_on_compare_match_B 0x04
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#endif |