#ifndef _AVR_MACROS_H_
#define _AVR_MACROS_H_

//// Compare Output Mode for Channel A
#define TCCRnA_COMnA_disconnected	0x00
#define TCCRnA_COMnA_toggle			0x40
#define TCCRnA_COMnA_low			0x80
#define TCCRnA_COMnA_high 			0xf0
#define TCCRnA_COMnA_CLEAR			~ (	TCCRnA_COMnA_disconnected	\
									  	| TCCRnA_COMnA_toggle		\
									  	| TCCRnA_COMnA_low			\
									  	| TCCRnA_COMnA_high			)
// Compare Output Mode for Channel B
#define TCCRnA_COMnB_disconnected	0x00
#define TCCRnA_COMnB_toggle			0x10
#define TCCRnA_COMnB_low			0x20
#define TCCRnA_COMnB_high 			0x30
#define TCCRnA_COMnB_CLEAR			~ ( TCCRnA_COMnB_disconnected	\
										| TCCRnA_COMnB_toggle		\
										| TCCRnA_COMnB_low			\
										| TCCRnA_COMnB_high			)

// Timer/CounterN Interrupt Mask Register
#define TIMSKn_ENABLE_INTERRUPT_on_nothing			0x00
#define TIMSKn_ENABLE_INTERRUPT_on_overflow			0x01
#define TIMSKn_ENABLE_INTERRUPT_on_compare_match_A	0x02
#define TIMSKn_ENABLE_INTERRUPT_on_compare_match_B	0x04
#define TIMSKn_ENABLE_INTERRUPT_CLEAR				~ ( TIMSKn_ENABLE_INTERRUPT_on_nothing 				\
														| TIMSKn_ENABLE_INTERRUPT_on_overflow 			\
														| TIMSKn_ENABLE_INTERRUPT_on_compare_match_A	\
														| TIMSKn_ENABLE_INTERRUPT_on_compare_match_B	)
/**********************************************************/

// Timer/Counter0 Control Register A
// Compare Output Mode for Channel A
#define TCCR0A_COM0A_disconnected	0x00
#define TCCR0A_COM0A_toggle			0x40
#define TCCR0A_COM0A_low			0x80
#define TCCR0A_COM0A_high 			0xf0
// Compare Output Mode for Channel B
#define TCCR0A_COM0B_disconnected	0x00
#define TCCR0A_COM0B_toggle			0x10
#define TCCR0A_COM0B_low			0x20
#define TCCR0A_COM0B_high 			0x30

// Timer/Counter0 Control Register B
// Clock Select 0 (prescaler)
#define TCCR0B_CS0_stopped			0x00
#define TCCR0B_CS0_prescale1 		0x01
#define TCCR0B_CS0_prescale8		0x02
#define TCCR0B_CS0_prescale64		0x03
#define TCCR0B_CS0_prescale256		0x04
#define TCCR0B_CS0_prescale1024		0x05
#define TCCR0B_CS0_falling_on_T0	0x06
#define TCCR0B_CS0_rising_on_T0		0x07

// Timer/Counter0 Interrupt Mask Register
#define TIMSK0_ENABLE_INTERRUPT_on_nothing			0x00
#define TIMSK0_ENABLE_INTERRUPT_on_overflow			0x01
#define TIMSK0_ENABLE_INTERRUPT_on_compare_match_A	0x02
#define TIMSK0_ENABLE_INTERRUPT_on_compare_match_B	0x04


// Timer/Counter1 Control Register A
// Compare Output Mode for Channel A
#define TCCR1A_COM1A_disconnected	0x00
#define TCCR1A_COM1A_toggle			0x40
#define TCCR1A_COM1A_low			0x80
#define TCCR1A_COM1A_high 			0xf0
// Compare Output Mode for Channel B
#define TCCR1A_COM1B_disconnected	0x00
#define TCCR1A_COM1B_toggle			0x10
#define TCCR1A_COM1B_low			0x20
#define TCCR1A_COM1B_high 			0x30

// Timer/Counter1 Control Register B
// Clock Select 1 (prescaler)
#define TCCR1B_CS1_stopped			0x00
#define TCCR1B_CS1_prescale1 		0x01
#define TCCR1B_CS1_prescale8		0x02
#define TCCR1B_CS1_prescale64		0x03
#define TCCR1B_CS1_prescale256		0x04
#define TCCR1B_CS1_prescale1024		0x05
#define TCCR1B_CS1_falling_on_T1	0x06
#define TCCR1B_CS1_rising_on_T1		0x07

// Timer/Counter1 Interrupt Mask Register
#define TIMSK1_ENABLE_INTERRUPT_on_nothing			0x00
#define TIMSK1_ENABLE_INTERRUPT_on_overflow			0x01
#define TIMSK1_ENABLE_INTERRUPT_on_compare_match_A	0x02
#define TIMSK1_ENABLE_INTERRUPT_on_compare_match_B	0x04


// Timer/Counter2 Control Register A
// Compare Output Mode for Channel A
#define TCCR2A_COM2A_disconnected	0x00
#define TCCR2A_COM2A_toggle			0x40
#define TCCR2A_COM2A_low			0x80
#define TCCR2A_COM2A_high 			0xf0
// Compare Output Mode for Channel B
#define TCCR2A_COM2B_disconnected	0x00
#define TCCR2A_COM2B_toggle			0x10
#define TCCR2A_COM2B_low			0x20
#define TCCR2A_COM2B_high 			0x30

// Timer/Counter1 Control Register B
// Clock Select 1 (prescaler)
#define TCCR2B_CS2_stopped			0x00
#define TCCR2B_CS2_prescale1 		0x01
#define TCCR2B_CS2_prescale8		0x02
#define TCCR2B_CS2_prescale32		0x03
#define TCCR2B_CS2_prescale64		0x04
#define TCCR2B_CS2_prescale128		0x05
#define TCCR2B_CS2_prescale256		0x06
#define TCCR2B_CS2_prescale1024		0x07

// Timer/Counter1 Interrupt Mask Register
#define TIMSK2_ENABLE_INTERRUPT_on_nothing			0x00
#define TIMSK2_ENABLE_INTERRUPT_on_overflow			0x01
#define TIMSK2_ENABLE_INTERRUPT_on_compare_match_A	0x02
#define TIMSK2_ENABLE_INTERRUPT_on_compare_match_B	0x04

#endif