Partially implement the Accu
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parent
1bdbf7a7e7
commit
ad6f5a5854
7
makefile
7
makefile
@ -1,8 +1,8 @@
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#-------------Makro-Part------------------
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CC = gcc
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CFLAGS = -Wall -std=c99
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CFLAGS = -Wall -pedantic -std=c99
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LDFLAGs =
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DEBUG =
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DEBUG = -DNDEBUG
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VPATH = src src/debug
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@ -21,5 +21,4 @@ debug.o : debug.c debug.h
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$(CC) $(DEBUG) $(CFLAGS) -o $@ -c $<
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clean :
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rm -f *.o
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rm -f *.o coredump*.toy
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BIN
src/.main.c.swp
Normal file
BIN
src/.main.c.swp
Normal file
Binary file not shown.
BIN
src/.toy.h.swp
Normal file
BIN
src/.toy.h.swp
Normal file
Binary file not shown.
23
src/main.c
23
src/main.c
@ -1,31 +1,40 @@
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#include "toy.h"
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#include "./debug/debug.h"
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#include<assert.h>
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#ifndef NDEBUG
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#define DEBUG
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#endif
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int main(int argc, char *argv[])
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{
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uint16_t ram[RAM_SIZE];
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uint16_t ir;
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uint16_t ir=0;
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uint8_t op_code;
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uint16_t pc = 0;
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uint16_t accu = 0;
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int data_addr=0;
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bool run = true;
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if(initialise_ram(ram,argc,argv)==-1) return 1;
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// makeHexDump(true,ram);
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// while(run && pc<(RAM_SIZE-1))
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// {
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ir = ram[2];
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pc++;
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ir = ram[pc];
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op_code = get_opcode(ir);
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printf("OP Code: %u\n",op_code);
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data_addr=find_data(ir);
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#ifdef DEBUG
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printf("OP Code: %u\n",op_code);
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printf("Adresse: %d\n",data_addr);
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makeHexDump(true,ram);
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#endif
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if(execute(op_code,data_addr,*ram))
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pc=data_addr(ram[pc]);
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else pc++;
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// }
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return 0;
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}
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26
src/toy.c
26
src/toy.c
@ -5,7 +5,6 @@ int initialise_ram(uint16_t *ram, int argc, char **argv )
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{
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//open Input Stream
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FILE *fp;
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int j=0;
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char tempS[CPU_WORD_SIZE+1]; //+1 for "\0"
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@ -66,4 +65,29 @@ int find_data(uint16_t instruction)
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return instr;
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}
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bool execute(uint8_t op_code, int data_addr, uint16_t *ram) // jump when 1
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{
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//vorsicht uint16 und Zweierkomplement noch nicht stringent !!!
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//Vorsicht bool ops bei sigend int typs sind undefiniert !
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static uint16_t accu;
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switch(op_code)
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{
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case 0: ram[data_addr]=accu; break;
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case 1: accu=ram[data_addr]; break;
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// case 2: if(!accu) break;
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case 3: accu=accu + ram[data_addr]; break;
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case 4: accu=accu - ram[data_addr]; break;
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case 5: accu=accu | ram[data_addr]; break;
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case 6: accu=accu & ram[data_addr]; break;
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case 7: accu=accu & ram[data_addr]; break;
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case 8: break;
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case 9: break;
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case 10: break;
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case 11: break;
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case 12: break;
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case 13: break;
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case 14: break;
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case 15: break;
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}
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