library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity control_logic is
end control_logic;

architecture test of control_logic is
    component main
        generic (
            FIRST: boolean
        );
        port (
            func: in std_logic_vector(3 downto 0);
            accu: in std_logic_vector(7 downto 0);
            ram: in std_logic_vector(7 downto 0);
            carry_in: in std_logic;
            result: out std_logic_vector(7 downto 0);
            carry_out: out std_logic
        );
    end component;

    type ram_type is array(0 to 4095) of std_logic_vector(15 downto 0);

    signal clk: std_logic;
    signal first: boolean := false;

    signal acc: std_logic_vector(15 downto 0) := (others => '0');
    signal ir: std_logic_vector(15 downto 0) := (others => '0');
    signal ram: ram_type := (
         0 => "0001000000001010",
         1 => "0011000000001000",
         2 => "0000000000001010",
         3 => "1011000000000000",
         4 => "0010000000000000",
         5 => "0000000000000000",
         6 => "0000000000000101",
         7 => "0000000000000111",
         8 => "0001001110001000",
         9 => "0000000000000000",
        10 => "0000000000000000",
        others => (others => '0')
    );
    signal pc:  std_logic_vector(11 downto 0) := (others => '0');

    signal data_out: std_logic_vector(15 downto 0);
    signal data_in: std_logic_vector(15 downto 0);
    signal carry_propagation: std_logic;
    signal addr: std_logic_vector(11 downto 0);
    signal op: std_logic_vector(3 downto 0);

    signal write_ram: std_logic;
    signal write_pc: std_logic;
    signal inc_pc: std_logic;
    signal ram_addr_ir: std_logic;
    signal write_ir: std_logic;
    signal write_acc: std_logic;


begin
    op <= ir(15 downto 12);
    addr <= ir(11 downto 0) when ram_addr_ir = '1' else pc;
    data_out <= ram(to_integer(unsigned(addr)));

    alu1: main generic map (
        FIRST => true
    ) port map (
        func => op,
        accu => acc(7 downto 0),
        ram => data_out(7 downto 0),
        carry_in => '0',
        result => data_in(7 downto 0),
        carry_out => carry_propagation
    );

    alu2: main generic map (
        FIRST => false
    ) port map (
        func => op,
        accu => acc(15 downto 8),
        ram => data_out(15 downto 8),
        carry_in => carry_propagation,
        result => data_in(15 downto 8),
        carry_out => open
    );

    process(clk)
    begin
        if rising_edge(clk) then
            if write_acc = '1' then
                acc <= data_in;
            end if;
            if write_ir = '1' then
                ir <= data_out;
            end if;
            if write_ram = '1' then
                ram(to_integer(unsigned(addr))) <= data_in;
            end if;
            if write_pc = '1' then
                pc <= ir(11 downto 0);
            elsif inc_pc = '1' then
                pc <= std_logic_vector(unsigned(pc) + 1);
            end if;
        end if;
    end process;

    process(first, op, acc)
    begin
        write_ram <= '0';
        write_pc <= '0';
        inc_pc <= '0';
        ram_addr_ir <= '1';
        write_ir <= '0';
        write_acc <= '1';

        if first then
            if op = "0000" then
                write_ram <= '1';
            end if;
            if acc = "0000000000000000" and op = "0010" then
                write_pc <= '1';
            end if;
            if op = "0000" or op = "0010" or op(3 downto 2) = "11" then
                write_acc <= '0';
            end if;
        else
            inc_pc <= '1';
            ram_addr_ir <= '0';
            write_ir <= '1';
            write_acc <= '0';
        end if;
    end process;

    process(clk)
    begin
        if rising_edge(clk) then
            first <= not first;
        end if;
    end process;

    process
    begin
        clk <= '1';
        wait for 1us;
        clk <= '0';
        wait for 1us;
    end process;
end test;