library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;

entity adder is
    generic (
        WIDTH: integer
    );
    port (
        x: in std_logic_vector(WIDTH-1 downto 0);
        y: in std_logic_vector(WIDTH-1 downto 0);
        cin: in std_logic;
        sum: out std_logic_vector(WIDTH-1 downto 0);
        cout: out std_logic
    );
end adder;

architecture rtl of adder is
    signal result: unsigned(WIDTH downto 0);
begin

    result <= resize(unsigned(x), WIDTH+1) +
              resize(unsigned(y), WIDTH+1) +
              ("" & cin);

    sum <= std_logic_vector(result(WIDTH-1 downto 0));
    cout <= result(WIDTH);

end rtl;