library ieee;

use ieee.std_logic_1164.all;

entity CPLD1 is
    port (
        func: in std_logic_vector(3 downto 0);
        accu: in std_logic_vector(5 downto 0);
        ram: in std_logic_vector(5 downto 0);
        result: out std_logic_vector(5 downto 0);
        carry_out: out std_logic
    );
end CPLD1;

architecture rtl of CPLD1 is
begin

    alu: entity work.alu generic map (
        WIDTH => 6,
        FIRST => true
    ) port map (
        func => func,
        accu => accu,
        ram => ram,
        carry_in => '0',
        result => result,
        carry_out => carry_out
    );

end rtl;