commit a5cb833b1d86f0f597fcf22d953cff6d7b7eb26f Author: Lena Date: Wed Mar 7 18:45:51 2018 +0100 Import unrouted mux12 board diff --git a/boards/mux12/mux12-cache.lib b/boards/mux12/mux12-cache.lib new file mode 100644 index 0000000..b3c2a8c --- /dev/null +++ b/boards/mux12/mux12-cache.lib @@ -0,0 +1,144 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 74LS257 +# +DEF 74LS257 U 0 10 Y Y 1 F N +F0 "U" 50 150 50 H V C CNN +F1 "74LS257" 50 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X GND 8 -350 -600 0 U 50 50 0 0 W N +X VCC 16 -350 600 0 U 50 50 0 0 W N +S -450 600 450 -600 0 1 0 N +X S 1 -750 -450 300 R 50 50 1 1 I +X I0a 2 -750 550 300 R 50 50 1 1 I +X I1a 3 -750 450 300 R 50 50 1 1 I +X Za 4 750 500 300 L 50 50 1 1 T +X I0b 5 -750 300 300 R 50 50 1 1 I +X I1b 6 -750 200 300 R 50 50 1 1 I +X Zb 7 750 250 300 L 50 50 1 1 T +X Zd 9 750 -250 300 L 50 50 1 1 T +X I1d 10 -750 -300 300 R 50 50 1 1 I +X I0d 11 -750 -200 300 R 50 50 1 1 I +X Zc 12 750 0 300 L 50 50 1 1 T +X I1c 13 -750 -50 300 R 50 50 1 1 I +X I0c 14 -750 50 300 R 50 50 1 1 I +X OE 15 -750 -550 300 R 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# Conn_01x04 +# +DEF Conn_01x04 J 0 40 Y N 1 F N +F0 "J" 0 200 50 H V C CNN +F1 "Conn_01x04" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:*_??x*mm* + Connector*:*1x??x*mm* + Pin?Header?Straight?1X* + Pin?Header?Angled?1X* + Socket?Strip?Straight?1X* + Socket?Strip?Angled?1X* +$ENDFPLIST +DRAW +S -50 -195 0 -205 1 1 6 N +S -50 -95 0 -105 1 1 6 N +S -50 5 0 -5 1 1 6 N +S -50 105 0 95 1 1 6 N +S -50 150 50 -250 1 1 10 f +X Pin_1 1 -200 100 150 R 50 50 1 1 P +X Pin_2 2 -200 0 150 R 50 50 1 1 P +X Pin_3 3 -200 -100 150 R 50 50 1 1 P +X Pin_4 4 -200 -200 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Conn_01x12 +# +DEF Conn_01x12 J 0 40 Y N 1 F N +F0 "J" 0 600 50 H V C CNN +F1 "Conn_01x12" 0 -700 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:*_??x*mm* + Connector*:*1x??x*mm* + Pin?Header?Straight?1X* + Pin?Header?Angled?1X* + Socket?Strip?Straight?1X* + Socket?Strip?Angled?1X* +$ENDFPLIST +DRAW +S -50 -595 0 -605 1 1 6 N +S -50 -495 0 -505 1 1 6 N +S -50 -395 0 -405 1 1 6 N +S -50 -295 0 -305 1 1 6 N +S -50 -195 0 -205 1 1 6 N +S -50 -95 0 -105 1 1 6 N +S -50 5 0 -5 1 1 6 N +S -50 105 0 95 1 1 6 N +S -50 205 0 195 1 1 6 N +S -50 305 0 295 1 1 6 N +S -50 405 0 395 1 1 6 N +S -50 505 0 495 1 1 6 N +S -50 550 50 -650 1 1 10 f +X Pin_1 1 -200 500 150 R 50 50 1 1 P +X Pin_2 2 -200 400 150 R 50 50 1 1 P +X Pin_3 3 -200 300 150 R 50 50 1 1 P +X Pin_4 4 -200 200 150 R 50 50 1 1 P +X Pin_5 5 -200 100 150 R 50 50 1 1 P +X Pin_6 6 -200 0 150 R 50 50 1 1 P +X Pin_7 7 -200 -100 150 R 50 50 1 1 P +X Pin_8 8 -200 -200 150 R 50 50 1 1 P +X Pin_9 9 -200 -300 150 R 50 50 1 1 P +X Pin_10 10 -200 -400 150 R 50 50 1 1 P +X Pin_11 11 -200 -500 150 R 50 50 1 1 P +X Pin_12 12 -200 -600 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# VCC +# +DEF VCC #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VCC" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VCC 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/boards/mux12/mux12.kicad_pcb b/boards/mux12/mux12.kicad_pcb new file mode 100644 index 0000000..326ab1a --- /dev/null +++ b/boards/mux12/mux12.kicad_pcb @@ -0,0 +1,618 @@ +(kicad_pcb (version 4) (host pcbnew 4.0.7) + + (general + (links 48) + (no_connects 48) + (area 137.492381 67.815 164.76762 135.485) + (thickness 1.6) + (drawings 0) + (tracks 0) + (zones 0) + (modules 7) + (nets 41) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (segment_width 0.2) + (edge_width 0.15) + (via_size 0.6) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.7 1.7) + (pad_drill 1) + (pad_to_mask_clearance 0.2) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x00030_80000001) + (usegerberextensions false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 "Net-(J1-Pad1)") + (net 2 "Net-(J1-Pad2)") + (net 3 "Net-(J1-Pad3)") + (net 4 "Net-(J1-Pad4)") + (net 5 "Net-(J1-Pad5)") + (net 6 "Net-(J1-Pad6)") + (net 7 "Net-(J1-Pad7)") + (net 8 "Net-(J1-Pad8)") + (net 9 "Net-(J1-Pad9)") + (net 10 "Net-(J1-Pad10)") + (net 11 "Net-(J1-Pad11)") + (net 12 "Net-(J1-Pad12)") + (net 13 "Net-(J2-Pad1)") + (net 14 "Net-(J2-Pad2)") + (net 15 "Net-(J2-Pad3)") + (net 16 "Net-(J2-Pad4)") + (net 17 "Net-(J2-Pad5)") + (net 18 "Net-(J2-Pad6)") + (net 19 "Net-(J2-Pad7)") + (net 20 "Net-(J2-Pad8)") + (net 21 "Net-(J2-Pad9)") + (net 22 "Net-(J2-Pad10)") + (net 23 "Net-(J2-Pad11)") + (net 24 "Net-(J2-Pad12)") + (net 25 /SEL) + (net 26 /~OE) + (net 27 VCC) + (net 28 GND) + (net 29 "Net-(J4-Pad1)") + (net 30 "Net-(J4-Pad2)") + (net 31 "Net-(J4-Pad3)") + (net 32 "Net-(J4-Pad4)") + (net 33 "Net-(J4-Pad5)") + (net 34 "Net-(J4-Pad6)") + (net 35 /Absicht_BITCH) + (net 36 "Net-(J4-Pad8)") + (net 37 "Net-(J4-Pad9)") + (net 38 "Net-(J4-Pad10)") + (net 39 "Net-(J4-Pad11)") + (net 40 "Net-(J4-Pad12)") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.6) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net /Absicht_BITCH) + (add_net /SEL) + (add_net /~OE) + (add_net GND) + (add_net "Net-(J1-Pad1)") + (add_net "Net-(J1-Pad10)") + (add_net "Net-(J1-Pad11)") + (add_net "Net-(J1-Pad12)") + (add_net "Net-(J1-Pad2)") + (add_net "Net-(J1-Pad3)") + (add_net "Net-(J1-Pad4)") + (add_net "Net-(J1-Pad5)") + (add_net "Net-(J1-Pad6)") + (add_net "Net-(J1-Pad7)") + (add_net "Net-(J1-Pad8)") + (add_net "Net-(J1-Pad9)") + (add_net "Net-(J2-Pad1)") + (add_net "Net-(J2-Pad10)") + (add_net "Net-(J2-Pad11)") + (add_net "Net-(J2-Pad12)") + (add_net "Net-(J2-Pad2)") + (add_net "Net-(J2-Pad3)") + (add_net "Net-(J2-Pad4)") + (add_net "Net-(J2-Pad5)") + (add_net "Net-(J2-Pad6)") + (add_net "Net-(J2-Pad7)") + (add_net "Net-(J2-Pad8)") + (add_net "Net-(J2-Pad9)") + (add_net "Net-(J4-Pad1)") + (add_net "Net-(J4-Pad10)") + (add_net "Net-(J4-Pad11)") + (add_net "Net-(J4-Pad12)") + (add_net "Net-(J4-Pad2)") + (add_net "Net-(J4-Pad3)") + (add_net "Net-(J4-Pad4)") + (add_net "Net-(J4-Pad5)") + (add_net "Net-(J4-Pad6)") + (add_net "Net-(J4-Pad8)") + (add_net "Net-(J4-Pad9)") + (add_net VCC) + ) + + (module Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm (layer B.Cu) (tedit 5AA01043) (tstamp 5AA008ED) + (at 142.24 104.14 180) + (descr "Through hole straight pin header, 1x12, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x12 2.54mm single row") + (path /5A9FFEB4) + (fp_text reference J1 (at 0 2.33 180) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_text value Conn_01x12 (at 0 -30.27 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1)) + (fp_line (start 1.27 1.27) (end 1.27 -29.21) (layer B.Fab) (width 0.1)) + (fp_line (start 1.27 -29.21) (end -1.27 -29.21) (layer B.Fab) (width 0.1)) + (fp_line (start -1.27 -29.21) (end -1.27 0.635) (layer B.Fab) (width 0.1)) + (fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1)) + (fp_line (start -1.33 -29.27) (end 1.33 -29.27) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.27) (end -1.33 -29.27) (layer B.SilkS) (width 0.12)) + (fp_line (start 1.33 -1.27) (end 1.33 -29.27) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.8 1.8) (end -1.8 -29.75) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.8 -29.75) (end 1.8 -29.75) (layer B.CrtYd) (width 0.05)) + (fp_line (start 1.8 -29.75) (end 1.8 1.8) (layer B.CrtYd) (width 0.05)) + (fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05)) + (fp_text user %R (at 0 -13.97 450) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (pad 1 thru_hole circle (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 "Net-(J1-Pad1)")) + (pad 2 thru_hole oval (at 0 -2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 2 "Net-(J1-Pad2)")) + (pad 3 thru_hole oval (at 0 -5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 3 "Net-(J1-Pad3)")) + (pad 4 thru_hole oval (at 0 -7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 4 "Net-(J1-Pad4)")) + (pad 5 thru_hole oval (at 0 -10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 5 "Net-(J1-Pad5)")) + (pad 6 thru_hole oval (at 0 -12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 6 "Net-(J1-Pad6)")) + (pad 7 thru_hole oval (at 0 -15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 7 "Net-(J1-Pad7)")) + (pad 8 thru_hole oval (at 0 -17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 8 "Net-(J1-Pad8)")) + (pad 9 thru_hole oval (at 0 -20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 9 "Net-(J1-Pad9)")) + (pad 10 thru_hole oval (at 0 -22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 10 "Net-(J1-Pad10)")) + (pad 11 thru_hole oval (at 0 -25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 11 "Net-(J1-Pad11)")) + (pad 12 thru_hole oval (at 0 -27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 12 "Net-(J1-Pad12)")) + (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x12_Pitch2.54mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm (layer B.Cu) (tedit 5AA01016) (tstamp 5AA008FD) + (at 142.24 71.12 180) + (descr "Through hole straight pin header, 1x12, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x12 2.54mm single row") + (path /5A9FFDF1) + (fp_text reference J2 (at 0 2.33 180) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_text value Conn_01x12 (at 0 -30.27 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1)) + (fp_line (start 1.27 1.27) (end 1.27 -29.21) (layer B.Fab) (width 0.1)) + (fp_line (start 1.27 -29.21) (end -1.27 -29.21) (layer B.Fab) (width 0.1)) + (fp_line (start -1.27 -29.21) (end -1.27 0.635) (layer B.Fab) (width 0.1)) + (fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1)) + (fp_line (start -1.33 -29.27) (end 1.33 -29.27) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.27) (end -1.33 -29.27) (layer B.SilkS) (width 0.12)) + (fp_line (start 1.33 -1.27) (end 1.33 -29.27) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.8 1.8) (end -1.8 -29.75) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.8 -29.75) (end 1.8 -29.75) (layer B.CrtYd) (width 0.05)) + (fp_line (start 1.8 -29.75) (end 1.8 1.8) (layer B.CrtYd) (width 0.05)) + (fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05)) + (fp_text user %R (at 0 -13.97 450) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (pad 1 thru_hole circle (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 13 "Net-(J2-Pad1)")) + (pad 2 thru_hole oval (at 0 -2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 14 "Net-(J2-Pad2)")) + (pad 3 thru_hole oval (at 0 -5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 15 "Net-(J2-Pad3)")) + (pad 4 thru_hole oval (at 0 -7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 16 "Net-(J2-Pad4)")) + (pad 5 thru_hole oval (at 0 -10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 17 "Net-(J2-Pad5)")) + (pad 6 thru_hole oval (at 0 -12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 18 "Net-(J2-Pad6)")) + (pad 7 thru_hole oval (at 0 -15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 19 "Net-(J2-Pad7)")) + (pad 8 thru_hole oval (at 0 -17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 20 "Net-(J2-Pad8)")) + (pad 9 thru_hole oval (at 0 -20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 21 "Net-(J2-Pad9)")) + (pad 10 thru_hole oval (at 0 -22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 22 "Net-(J2-Pad10)")) + (pad 11 thru_hole oval (at 0 -25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 23 "Net-(J2-Pad11)")) + (pad 12 thru_hole oval (at 0 -27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 24 "Net-(J2-Pad12)")) + (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x12_Pitch2.54mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x04_Pitch2.54mm (layer B.Cu) (tedit 5AA00FF6) (tstamp 5AA00905) + (at 160.02 124.46 180) + (descr "Through hole straight pin header, 1x04, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x04 2.54mm single row") + (path /5A9FFF5C) + (fp_text reference J3 (at 0 2.33 180) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_text value Conn_01x04 (at 0 -9.95 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1)) + (fp_line (start 1.27 1.27) (end 1.27 -8.89) (layer B.Fab) (width 0.1)) + (fp_line (start 1.27 -8.89) (end -1.27 -8.89) (layer B.Fab) (width 0.1)) + (fp_line (start -1.27 -8.89) (end -1.27 0.635) (layer B.Fab) (width 0.1)) + (fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1)) + (fp_line (start -1.33 -8.95) (end 1.33 -8.95) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.27) (end -1.33 -8.95) (layer B.SilkS) (width 0.12)) + (fp_line (start 1.33 -1.27) (end 1.33 -8.95) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.8 1.8) (end -1.8 -9.4) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.8 -9.4) (end 1.8 -9.4) (layer B.CrtYd) (width 0.05)) + (fp_line (start 1.8 -9.4) (end 1.8 1.8) (layer B.CrtYd) (width 0.05)) + (fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05)) + (fp_text user %R (at 0 -3.81 450) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (pad 1 thru_hole circle (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 25 /SEL)) + (pad 2 thru_hole oval (at 0 -2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 26 /~OE)) + (pad 3 thru_hole oval (at 0 -5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 27 VCC)) + (pad 4 thru_hole rect (at 0 -7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 28 GND)) + (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x04_Pitch2.54mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm (layer B.Cu) (tedit 5AA01030) (tstamp 5AA00915) + (at 160.02 88.9 180) + (descr "Through hole straight pin header, 1x12, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x12 2.54mm single row") + (path /5A9FFEF2) + (fp_text reference J4 (at 0 2.33 180) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_text value Conn_01x12 (at 0 -30.27 180) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1)) + (fp_line (start 1.27 1.27) (end 1.27 -29.21) (layer B.Fab) (width 0.1)) + (fp_line (start 1.27 -29.21) (end -1.27 -29.21) (layer B.Fab) (width 0.1)) + (fp_line (start -1.27 -29.21) (end -1.27 0.635) (layer B.Fab) (width 0.1)) + (fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1)) + (fp_line (start -1.33 -29.27) (end 1.33 -29.27) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.27) (end -1.33 -29.27) (layer B.SilkS) (width 0.12)) + (fp_line (start 1.33 -1.27) (end 1.33 -29.27) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.8 1.8) (end -1.8 -29.75) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.8 -29.75) (end 1.8 -29.75) (layer B.CrtYd) (width 0.05)) + (fp_line (start 1.8 -29.75) (end 1.8 1.8) (layer B.CrtYd) (width 0.05)) + (fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05)) + (fp_text user %R (at 0 -13.97 450) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (pad 1 thru_hole circle (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 29 "Net-(J4-Pad1)")) + (pad 2 thru_hole oval (at 0 -2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 30 "Net-(J4-Pad2)")) + (pad 3 thru_hole oval (at 0 -5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 31 "Net-(J4-Pad3)")) + (pad 4 thru_hole oval (at 0 -7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 32 "Net-(J4-Pad4)")) + (pad 5 thru_hole oval (at 0 -10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 33 "Net-(J4-Pad5)")) + (pad 6 thru_hole oval (at 0 -12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 34 "Net-(J4-Pad6)")) + (pad 7 thru_hole oval (at 0 -15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 35 /Absicht_BITCH)) + (pad 8 thru_hole oval (at 0 -17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 36 "Net-(J4-Pad8)")) + (pad 9 thru_hole oval (at 0 -20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 37 "Net-(J4-Pad9)")) + (pad 10 thru_hole oval (at 0 -22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 38 "Net-(J4-Pad10)")) + (pad 11 thru_hole oval (at 0 -25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 39 "Net-(J4-Pad11)")) + (pad 12 thru_hole oval (at 0 -27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 40 "Net-(J4-Pad12)")) + (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x12_Pitch2.54mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer F.Cu) (tedit 58CC8F64) (tstamp 5AA00929) + (at 152.4 81.28) + (descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SOIC 1.27") + (path /5A9FF14C) + (attr smd) + (fp_text reference U1 (at 0 -6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 74LS257 (at 0 6) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.9 0.9) (thickness 0.135))) + ) + (fp_line (start -0.95 -4.95) (end 1.95 -4.95) (layer F.Fab) (width 0.15)) + (fp_line (start 1.95 -4.95) (end 1.95 4.95) (layer F.Fab) (width 0.15)) + (fp_line (start 1.95 4.95) (end -1.95 4.95) (layer F.Fab) (width 0.15)) + (fp_line (start -1.95 4.95) (end -1.95 -3.95) (layer F.Fab) (width 0.15)) + (fp_line (start -1.95 -3.95) (end -0.95 -4.95) (layer F.Fab) (width 0.15)) + (fp_line (start -3.7 -5.25) (end -3.7 5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.7 -5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.7 -5.25) (end 3.7 -5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.7 5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.075 -5.075) (end -2.075 -5.05) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.075 -5.075) (end 2.075 -4.97) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.075 5.075) (end 2.075 4.97) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 5.075) (end -2.075 4.97) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 -5.075) (end 2.075 -5.075) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 5.075) (end 2.075 5.075) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 -5.05) (end -3.45 -5.05) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at -2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 25 /SEL)) + (pad 2 smd rect (at -2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 1 "Net-(J1-Pad1)")) + (pad 3 smd rect (at -2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 13 "Net-(J2-Pad1)")) + (pad 4 smd rect (at -2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 29 "Net-(J4-Pad1)")) + (pad 5 smd rect (at -2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 2 "Net-(J1-Pad2)")) + (pad 6 smd rect (at -2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 14 "Net-(J2-Pad2)")) + (pad 7 smd rect (at -2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 30 "Net-(J4-Pad2)")) + (pad 8 smd rect (at -2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 28 GND)) + (pad 9 smd rect (at 2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 32 "Net-(J4-Pad4)")) + (pad 10 smd rect (at 2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 16 "Net-(J2-Pad4)")) + (pad 11 smd rect (at 2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 4 "Net-(J1-Pad4)")) + (pad 12 smd rect (at 2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 31 "Net-(J4-Pad3)")) + (pad 13 smd rect (at 2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 15 "Net-(J2-Pad3)")) + (pad 14 smd rect (at 2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 3 "Net-(J1-Pad3)")) + (pad 15 smd rect (at 2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 26 /~OE)) + (pad 16 smd rect (at 2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 27 VCC)) + (model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer F.Cu) (tedit 58CC8F64) (tstamp 5AA0093D) + (at 152.4 101.6) + (descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SOIC 1.27") + (path /5A9FFC25) + (attr smd) + (fp_text reference U2 (at 0 -6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 74LS257 (at 0 6) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.9 0.9) (thickness 0.135))) + ) + (fp_line (start -0.95 -4.95) (end 1.95 -4.95) (layer F.Fab) (width 0.15)) + (fp_line (start 1.95 -4.95) (end 1.95 4.95) (layer F.Fab) (width 0.15)) + (fp_line (start 1.95 4.95) (end -1.95 4.95) (layer F.Fab) (width 0.15)) + (fp_line (start -1.95 4.95) (end -1.95 -3.95) (layer F.Fab) (width 0.15)) + (fp_line (start -1.95 -3.95) (end -0.95 -4.95) (layer F.Fab) (width 0.15)) + (fp_line (start -3.7 -5.25) (end -3.7 5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.7 -5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.7 -5.25) (end 3.7 -5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.7 5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.075 -5.075) (end -2.075 -5.05) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.075 -5.075) (end 2.075 -4.97) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.075 5.075) (end 2.075 4.97) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 5.075) (end -2.075 4.97) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 -5.075) (end 2.075 -5.075) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 5.075) (end 2.075 5.075) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 -5.05) (end -3.45 -5.05) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at -2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 25 /SEL)) + (pad 2 smd rect (at -2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 5 "Net-(J1-Pad5)")) + (pad 3 smd rect (at -2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 17 "Net-(J2-Pad5)")) + (pad 4 smd rect (at -2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 33 "Net-(J4-Pad5)")) + (pad 5 smd rect (at -2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 6 "Net-(J1-Pad6)")) + (pad 6 smd rect (at -2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 18 "Net-(J2-Pad6)")) + (pad 7 smd rect (at -2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 34 "Net-(J4-Pad6)")) + (pad 8 smd rect (at -2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 28 GND)) + (pad 9 smd rect (at 2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 36 "Net-(J4-Pad8)")) + (pad 10 smd rect (at 2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 20 "Net-(J2-Pad8)")) + (pad 11 smd rect (at 2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 8 "Net-(J1-Pad8)")) + (pad 12 smd rect (at 2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 35 /Absicht_BITCH)) + (pad 13 smd rect (at 2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 19 "Net-(J2-Pad7)")) + (pad 14 smd rect (at 2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 "Net-(J1-Pad7)")) + (pad 15 smd rect (at 2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 26 /~OE)) + (pad 16 smd rect (at 2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 27 VCC)) + (model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer F.Cu) (tedit 58CC8F64) (tstamp 5AA00951) + (at 152.4 124.46) + (descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SOIC 1.27") + (path /5A9FFD36) + (attr smd) + (fp_text reference U3 (at 0 -6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 74LS257 (at 0 6) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.9 0.9) (thickness 0.135))) + ) + (fp_line (start -0.95 -4.95) (end 1.95 -4.95) (layer F.Fab) (width 0.15)) + (fp_line (start 1.95 -4.95) (end 1.95 4.95) (layer F.Fab) (width 0.15)) + (fp_line (start 1.95 4.95) (end -1.95 4.95) (layer F.Fab) (width 0.15)) + (fp_line (start -1.95 4.95) (end -1.95 -3.95) (layer F.Fab) (width 0.15)) + (fp_line (start -1.95 -3.95) (end -0.95 -4.95) (layer F.Fab) (width 0.15)) + (fp_line (start -3.7 -5.25) (end -3.7 5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.7 -5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.7 -5.25) (end 3.7 -5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.7 5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.075 -5.075) (end -2.075 -5.05) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.075 -5.075) (end 2.075 -4.97) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.075 5.075) (end 2.075 4.97) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 5.075) (end -2.075 4.97) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 -5.075) (end 2.075 -5.075) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 5.075) (end 2.075 5.075) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 -5.05) (end -3.45 -5.05) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at -2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 25 /SEL)) + (pad 2 smd rect (at -2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 9 "Net-(J1-Pad9)")) + (pad 3 smd rect (at -2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 21 "Net-(J2-Pad9)")) + (pad 4 smd rect (at -2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 37 "Net-(J4-Pad9)")) + (pad 5 smd rect (at -2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 10 "Net-(J1-Pad10)")) + (pad 6 smd rect (at -2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 22 "Net-(J2-Pad10)")) + (pad 7 smd rect (at -2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 38 "Net-(J4-Pad10)")) + (pad 8 smd rect (at -2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 28 GND)) + (pad 9 smd rect (at 2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 40 "Net-(J4-Pad12)")) + (pad 10 smd rect (at 2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 24 "Net-(J2-Pad12)")) + (pad 11 smd rect (at 2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 12 "Net-(J1-Pad12)")) + (pad 12 smd rect (at 2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 39 "Net-(J4-Pad11)")) + (pad 13 smd rect (at 2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 23 "Net-(J2-Pad11)")) + (pad 14 smd rect (at 2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 11 "Net-(J1-Pad11)")) + (pad 15 smd rect (at 2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 26 /~OE)) + (pad 16 smd rect (at 2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask) + (net 27 VCC)) + (model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + +) diff --git a/boards/mux12/mux12.pro b/boards/mux12/mux12.pro new file mode 100644 index 0000000..afc7ac7 --- /dev/null +++ b/boards/mux12/mux12.pro @@ -0,0 +1,63 @@ +update=2018-03-07T15:02:50 CET +version=1 +last_client=kicad +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=switches +LibName4=relays +LibName5=motors +LibName6=transistors +LibName7=conn +LibName8=linear +LibName9=regul +LibName10=74xx +LibName11=cmos4000 +LibName12=adc-dac +LibName13=memory +LibName14=xilinx +LibName15=microcontrollers +LibName16=dsp +LibName17=microchip +LibName18=analog_switches +LibName19=motorola +LibName20=texas +LibName21=intel +LibName22=audio +LibName23=interface +LibName24=digital-audio +LibName25=philips +LibName26=display +LibName27=cypress +LibName28=siliconi +LibName29=opto +LibName30=atmel +LibName31=contrib +LibName32=valves +[general] +version=1 diff --git a/boards/mux12/mux12.sch b/boards/mux12/mux12.sch new file mode 100644 index 0000000..fcbd410 --- /dev/null +++ b/boards/mux12/mux12.sch @@ -0,0 +1,440 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:switches +LIBS:relays +LIBS:motors +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:mux12-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 74LS257 U2 +U 1 1 5A9FFC25 +P 4000 3450 +F 0 "U2" H 4050 3600 50 0000 C CNN +F 1 "74LS257" H 4050 3300 50 0000 C CNN +F 2 "Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm" H 4000 3450 50 0001 C CNN +F 3 "" H 4000 3450 50 0001 C CNN + 1 4000 3450 + 1 0 0 -1 +$EndComp +$Comp +L 74LS257 U3 +U 1 1 5A9FFD36 +P 4000 4700 +F 0 "U3" H 4050 4850 50 0000 C CNN +F 1 "74LS257" H 4050 4550 50 0000 C CNN +F 2 "Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm" H 4000 4700 50 0001 C CNN +F 3 "" H 4000 4700 50 0001 C CNN + 1 4000 4700 + 1 0 0 -1 +$EndComp +$Comp +L Conn_01x12 J2 +U 1 1 5A9FFDF1 +P 1400 4100 +F 0 "J2" H 1400 4700 50 0000 C CNN +F 1 "Conn_01x12" H 1400 3400 50 0000 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm" H 1400 4100 50 0001 C CNN +F 3 "" H 1400 4100 50 0001 C CNN + 1 1400 4100 + -1 0 0 -1 +$EndComp +$Comp +L Conn_01x12 J1 +U 1 1 5A9FFEB4 +P 1400 2450 +F 0 "J1" H 1400 3050 50 0000 C CNN +F 1 "Conn_01x12" H 1400 1750 50 0000 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm" H 1400 2450 50 0001 C CNN +F 3 "" H 1400 2450 50 0001 C CNN + 1 1400 2450 + -1 0 0 -1 +$EndComp +$Comp +L Conn_01x12 J4 +U 1 1 5A9FFEF2 +P 6550 3300 +F 0 "J4" H 6550 3900 50 0000 C CNN +F 1 "Conn_01x12" H 6550 2600 50 0000 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm" H 6550 3300 50 0001 C CNN +F 3 "" H 6550 3300 50 0001 C CNN + 1 6550 3300 + 1 0 0 -1 +$EndComp +$Comp +L Conn_01x04 J3 +U 1 1 5A9FFF5C +P 1750 5900 +F 0 "J3" H 1750 6100 50 0000 C CNN +F 1 "Conn_01x04" H 1750 5600 50 0000 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x04_Pitch2.54mm" H 1750 5900 50 0001 C CNN +F 3 "" H 1750 5900 50 0001 C CNN + 1 1750 5900 + -1 0 0 -1 +$EndComp +$Comp +L 74LS257 U1 +U 1 1 5A9FF14C +P 4000 2200 +F 0 "U1" H 4050 2350 50 0000 C CNN +F 1 "74LS257" H 4050 2050 50 0000 C CNN +F 2 "Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm" H 4000 2200 50 0001 C CNN +F 3 "" H 4000 2200 50 0001 C CNN + 1 4000 2200 + 1 0 0 -1 +$EndComp +Text Label 3000 2650 0 60 ~ 0 +SEL +Text Label 3000 3900 0 60 ~ 0 +SEL +Text Label 3000 5150 0 60 ~ 0 +SEL +Text Label 3000 5250 0 60 ~ 0 +~OE +Text Label 3000 4000 0 60 ~ 0 +~OE +Text Label 3000 2750 0 60 ~ 0 +~OE +Text Label 2350 5900 0 60 ~ 0 +~OE +Text Label 2250 5800 0 60 ~ 0 +SEL +$Comp +L VCC #PWR01 +U 1 1 5AA01301 +P 2550 6000 +F 0 "#PWR01" H 2550 5850 50 0001 C CNN +F 1 "VCC" H 2550 6150 50 0000 C CNN +F 2 "" H 2550 6000 50 0001 C CNN +F 3 "" H 2550 6000 50 0001 C CNN + 1 2550 6000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5AA0132A +P 2700 6100 +F 0 "#PWR02" H 2700 5850 50 0001 C CNN +F 1 "GND" H 2700 5950 50 0000 C CNN +F 2 "" H 2700 6100 50 0001 C CNN +F 3 "" H 2700 6100 50 0001 C CNN + 1 2700 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 3700 4750 3700 +Wire Wire Line + 6100 3500 6100 3700 +Wire Wire Line + 6350 3500 6100 3500 +Wire Wire Line + 6150 3600 6350 3600 +Wire Wire Line + 6150 4200 6150 3600 +Wire Wire Line + 4750 4200 6150 4200 +Wire Wire Line + 6200 3700 6350 3700 +Wire Wire Line + 6200 4450 6200 3700 +Wire Wire Line + 4750 4450 6200 4450 +Wire Wire Line + 6250 3800 6350 3800 +Wire Wire Line + 6250 4700 6250 3800 +Wire Wire Line + 4750 4700 6250 4700 +Wire Wire Line + 6300 4950 4750 4950 +Wire Wire Line + 6300 3900 6300 4950 +Wire Wire Line + 6350 3900 6300 3900 +Wire Wire Line + 1950 6100 2700 6100 +Wire Wire Line + 1950 6000 2550 6000 +Wire Wire Line + 1950 5800 2250 5800 +Wire Wire Line + 1950 5900 2350 5900 +Wire Wire Line + 3000 5150 3250 5150 +Wire Wire Line + 3000 5250 3250 5250 +Wire Wire Line + 3000 4000 3250 4000 +Wire Wire Line + 3000 3900 3250 3900 +Wire Wire Line + 3000 2750 3250 2750 +Wire Wire Line + 3000 2650 3250 2650 +Wire Wire Line + 3250 4450 3250 4400 +Wire Wire Line + 1900 4450 3250 4450 +Wire Wire Line + 2450 5000 3250 5000 +Wire Wire Line + 2450 4700 2450 5000 +Wire Wire Line + 1600 4700 2450 4700 +Wire Wire Line + 2300 3600 1600 3600 +Wire Wire Line + 2300 3600 2300 1750 +Wire Wire Line + 2300 1750 3250 1750 +Wire Wire Line + 2350 2000 3250 2000 +Wire Wire Line + 2350 3700 2350 2000 +Wire Wire Line + 1600 3700 2350 3700 +Wire Wire Line + 2400 3800 1600 3800 +Wire Wire Line + 2400 2250 2400 3800 +Wire Wire Line + 3250 2250 2400 2250 +Wire Wire Line + 2450 2500 3250 2500 +Wire Wire Line + 2450 3900 2450 2500 +Wire Wire Line + 1600 3900 2450 3900 +Wire Wire Line + 2500 3000 3250 3000 +Wire Wire Line + 2500 4000 2500 3000 +Wire Wire Line + 1600 4000 2500 4000 +Wire Wire Line + 2550 4100 1600 4100 +Wire Wire Line + 2550 3250 2550 4100 +Wire Wire Line + 3250 3250 2550 3250 +Wire Wire Line + 2600 3500 3250 3500 +Wire Wire Line + 2600 4200 2600 3500 +Wire Wire Line + 1600 4200 2600 4200 +Wire Wire Line + 2650 4300 1600 4300 +Wire Wire Line + 2650 3750 2650 4300 +Wire Wire Line + 3250 3750 2650 3750 +Wire Wire Line + 2700 4400 1600 4400 +Wire Wire Line + 2700 4250 2700 4400 +Wire Wire Line + 3250 4250 2700 4250 +Wire Wire Line + 2550 4750 3250 4750 +Wire Wire Line + 2550 4600 2550 4750 +Wire Wire Line + 1600 4600 2550 4600 +Wire Wire Line + 1600 4500 3250 4500 +Wire Wire Line + 1950 1650 3250 1650 +Wire Wire Line + 1950 1950 1950 1650 +Wire Wire Line + 1600 1950 1950 1950 +Wire Wire Line + 1800 3050 1600 3050 +Wire Wire Line + 1800 3050 1800 4900 +Wire Wire Line + 1800 4900 3250 4900 +Wire Wire Line + 1850 4650 3250 4650 +Wire Wire Line + 1850 2950 1850 4650 +Wire Wire Line + 1600 2950 1850 2950 +Wire Wire Line + 1900 2850 1600 2850 +Wire Wire Line + 1900 4450 1900 2850 +Wire Wire Line + 1950 4150 3250 4150 +Wire Wire Line + 1950 2750 1950 4150 +Wire Wire Line + 1600 2750 1950 2750 +Wire Wire Line + 2000 3650 3250 3650 +Wire Wire Line + 2000 2650 2000 3650 +Wire Wire Line + 1600 2650 2000 2650 +Wire Wire Line + 2050 2550 1600 2550 +Wire Wire Line + 2050 3400 2050 2550 +Wire Wire Line + 3250 3400 2050 3400 +Wire Wire Line + 2100 3150 3250 3150 +Wire Wire Line + 2100 2450 2100 3150 +Wire Wire Line + 1600 2450 2100 2450 +Wire Wire Line + 2150 2350 1600 2350 +Wire Wire Line + 2150 2900 2150 2350 +Wire Wire Line + 3250 2900 2150 2900 +Wire Wire Line + 2200 2250 1600 2250 +Wire Wire Line + 2200 2400 2200 2250 +Wire Wire Line + 3250 2400 2200 2400 +Wire Wire Line + 2050 1900 3250 1900 +Wire Wire Line + 2050 2050 2050 1900 +Wire Wire Line + 1600 2050 2050 2050 +Wire Wire Line + 1600 2150 3250 2150 +Wire Wire Line + 6350 2800 6300 2800 +Wire Wire Line + 6300 2800 6300 1700 +Wire Wire Line + 6300 1700 4750 1700 +Wire Wire Line + 6350 2900 6250 2900 +Wire Wire Line + 6250 2900 6250 1950 +Wire Wire Line + 6250 1950 4750 1950 +Wire Wire Line + 4750 2200 6200 2200 +Wire Wire Line + 6200 2200 6200 3000 +Wire Wire Line + 6200 3000 6350 3000 +Wire Wire Line + 6350 3100 6150 3100 +Wire Wire Line + 6150 3100 6150 2450 +Wire Wire Line + 6150 2450 4750 2450 +Wire Wire Line + 4750 2950 6100 2950 +Wire Wire Line + 6100 2950 6100 3200 +Wire Wire Line + 6100 3200 6350 3200 +Wire Wire Line + 6350 3300 6050 3300 +Wire Wire Line + 6050 3300 6050 3200 +Wire Wire Line + 6050 3200 4750 3200 +Wire Wire Line + 4750 3450 5900 3450 +Wire Wire Line + 5900 3450 5900 3400 +Wire Wire Line + 5900 3400 6350 3400 +Text Label 5350 3450 0 60 ~ 0 +Absicht_BITCH +$Comp +L PWR_FLAG #FLG03 +U 1 1 5AA01E5B +P 4300 5800 +F 0 "#FLG03" H 4300 5875 50 0001 C CNN +F 1 "PWR_FLAG" H 4300 5950 50 0000 C CNN +F 2 "" H 4300 5800 50 0001 C CNN +F 3 "" H 4300 5800 50 0001 C CNN + 1 4300 5800 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG04 +U 1 1 5AA01E84 +P 5200 5750 +F 0 "#FLG04" H 5200 5825 50 0001 C CNN +F 1 "PWR_FLAG" H 5200 5900 50 0000 C CNN +F 2 "" H 5200 5750 50 0001 C CNN +F 3 "" H 5200 5750 50 0001 C CNN + 1 5200 5750 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 5AA01F39 +P 4300 5800 +F 0 "#PWR05" H 4300 5550 50 0001 C CNN +F 1 "GND" H 4300 5650 50 0000 C CNN +F 2 "" H 4300 5800 50 0001 C CNN +F 3 "" H 4300 5800 50 0001 C CNN + 1 4300 5800 + 1 0 0 -1 +$EndComp +$Comp +L VCC #PWR06 +U 1 1 5AA01F62 +P 5200 5750 +F 0 "#PWR06" H 5200 5600 50 0001 C CNN +F 1 "VCC" H 5200 5900 50 0000 C CNN +F 2 "" H 5200 5750 50 0001 C CNN +F 3 "" H 5200 5750 50 0001 C CNN + 1 5200 5750 + -1 0 0 1 +$EndComp +$EndSCHEMATC