/dts-v1/;

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "freechips,rocketchip-unknown-dev";
	model = "freechips,rocketchip-unknown";
	aliases {
		serial0 = &L8;
	};
	L15: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		L5: cpu@0 {
			clock-frequency = <60000000>;
			compatible = "sifive,rocket0", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <4096>;
			d-tlb-sets = <1>;
			d-tlb-size = <4>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <4096>;
			i-tlb-sets = <1>;
			i-tlb-size = <4>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&L12>;
			reg = <0>;
			riscv,isa = "rv64imafdc";
			status = "okay";
			timebase-frequency = <1000000>;
			tlb-split;
			L3: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};
	};
	L12: memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;
	};
	L14: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
		ranges;
		sysclk: sysclk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <60000000>;
		}; 
		L1: clint@2000000 {
			compatible = "riscv,clint0";
			interrupts-extended = <&L3 3 &L3 7>;
			reg = <0x2000000 0x10000>;
			reg-names = "control";
		};
		L2: debug-controller@0 {
			compatible = "sifive,debug-013", "riscv,debug-013";
			interrupts-extended = <&L3 65535>;
			reg = <0x0 0x1000>;
			reg-names = "control";
		};
		L7: error-device@3000 {
			compatible = "sifive,error0";
			reg = <0x3000 0x1000>;
			reg-names = "mem";
		};
		L11: gpio@64002000 {
			compatible = "sifive,gpio0";
			interrupt-parent = <&L0>;
			interrupts = <3 4 5 6 7 8 9 10>;
			reg = <0x64002000 0x1000>;
			reg-names = "control";
		};
		L0: interrupt-controller@c000000 {
			#interrupt-cells = <1>;
			compatible = "riscv,plic0";
			interrupt-controller;
			interrupts-extended = <&L3 11 &L3 9>;
			reg = <0xc000000 0x4000000>;
			reg-names = "control";
			riscv,max-priority = <7>;
			riscv,ndev = <10>;
		};
		L6: rom@10000 {
			compatible = "sifive,maskrom0";
			reg = <0x10000 0x2000>;
			reg-names = "mem";
		};
		L8: serial@64000000 {
			compatible = "sifive,uart0";
			interrupt-parent = <&L0>;
			interrupts = <1>;
			reg = <0x64000000 0x1000>;
			reg-names = "control";
			clocks = <&sysclk 0>;
		};
		L10: spi@64001000 {
			compatible = "sifive,spi0";
			interrupt-parent = <&L0>;
			interrupts = <2>;
			reg = <0x64001000 0x1000>;
			reg-names = "control";
			clocks = <&sysclk 0>;
			#address-cells = <1>;
			#size-cells = <0>;

			mmc@0 {
				compatible = "mmc-spi-slot";
				reg = <0x0>;
				spi-max-frequency = <0x1312d00>;
				voltage-ranges = <0xce4 0xce4>;
				disable-wp;
			};
		};
		L9: serial@64003000 {
			compatible = "klemens,terminal0";
			reg = <0x64003000 0x1000>;
			reg-names = "control";
			clocks = <&sysclk 0>;
		};
	};
};