From f9b72609f16308d1a5933162324d64ae7993e41b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= Date: Tue, 5 Jun 2018 16:00:30 +0200 Subject: [PATCH] Import clock definition files --- project/ise/ml507_ddr2_clock.v | 93 +++++++++++++++++++++++++++++ project/ise/ml507_dvi_clock.v | 81 +++++++++++++++++++++++++ project/ise/ml507_sys_clock.v | 81 +++++++++++++++++++++++++ project/ise/risc-v-workstation.xise | 12 ++++ 4 files changed, 267 insertions(+) create mode 100644 project/ise/ml507_ddr2_clock.v create mode 100644 project/ise/ml507_dvi_clock.v create mode 100644 project/ise/ml507_sys_clock.v diff --git a/project/ise/ml507_ddr2_clock.v b/project/ise/ml507_ddr2_clock.v new file mode 100644 index 0000000..e404edc --- /dev/null +++ b/project/ise/ml507_ddr2_clock.v @@ -0,0 +1,93 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.7 +// \ \ Application : xaw2verilog +// / / Filename : ml507_ddr2_clock.v +// /___/ /\ Timestamp : 05/10/2018 01:18:22 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -intstyle /repos/master/riscv_test/ipcore_dir/ml507_ddr2_clock.xaw -st ml507_ddr2_clock.v +//Design Name: ml507_ddr2_clock +//Device: xc5vfx70t-1ff1136 +// +// Module ml507_ddr2_clock +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +`timescale 1ns / 1ps + +module ml507_ddr2_clock(CLKIN_N_IN, + CLKIN_P_IN, + CLKDV_OUT, + CLKIN_IBUFGDS_OUT, + CLK0_OUT, + CLK90_OUT, + LOCKED_OUT); + + input CLKIN_N_IN; + input CLKIN_P_IN; + output CLKDV_OUT; + output CLKIN_IBUFGDS_OUT; + output CLK0_OUT; + output CLK90_OUT; + output LOCKED_OUT; + + wire CLKDV_BUF; + wire CLKFB_IN; + wire CLKIN_IBUFGDS; + wire CLK0_BUF; + wire CLK90_BUF; + wire GND_BIT; + wire [6:0] GND_BUS_7; + wire [15:0] GND_BUS_16; + + assign GND_BIT = 0; + assign GND_BUS_7 = 7'b0000000; + assign GND_BUS_16 = 16'b0000000000000000; + assign CLKIN_IBUFGDS_OUT = CLKIN_IBUFGDS; + assign CLK0_OUT = CLKFB_IN; + BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF), + .O(CLKDV_OUT)); + IBUFGDS CLKIN_IBUFGDS_INST (.I(CLKIN_P_IN), + .IB(CLKIN_N_IN), + .O(CLKIN_IBUFGDS)); + BUFG CLK0_BUFG_INST (.I(CLK0_BUF), + .O(CLKFB_IN)); + BUFG CLK90_BUFG_INST (.I(CLK90_BUF), + .O(CLK90_OUT)); + DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1), + .CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_PERIOD(5.000), + .CLKOUT_PHASE_SHIFT("NONE"), .DCM_AUTOCALIBRATION("TRUE"), + .DCM_PERFORMANCE_MODE("MAX_SPEED"), + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("HIGH"), + .DLL_FREQUENCY_MODE("HIGH"), .DUTY_CYCLE_CORRECTION("TRUE"), + .FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"), + .SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN), + .CLKIN(CLKIN_IBUFGDS), + .DADDR(GND_BUS_7[6:0]), + .DCLK(GND_BIT), + .DEN(GND_BIT), + .DI(GND_BUS_16[15:0]), + .DWE(GND_BIT), + .PSCLK(GND_BIT), + .PSEN(GND_BIT), + .PSINCDEC(GND_BIT), + .RST(GND_BIT), + .CLKDV(CLKDV_BUF), + .CLKFX(), + .CLKFX180(), + .CLK0(CLK0_BUF), + .CLK2X(), + .CLK2X180(), + .CLK90(CLK90_BUF), + .CLK180(), + .CLK270(), + .DO(), + .DRDY(), + .LOCKED(LOCKED_OUT), + .PSDONE()); +endmodule diff --git a/project/ise/ml507_dvi_clock.v b/project/ise/ml507_dvi_clock.v new file mode 100644 index 0000000..eed6baa --- /dev/null +++ b/project/ise/ml507_dvi_clock.v @@ -0,0 +1,81 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.7 +// \ \ Application : xaw2verilog +// / / Filename : ml507_dvi_clock.v +// /___/ /\ Timestamp : 04/30/2018 22:20:54 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -intstyle /repos/master/riscv_test/ipcore_dir/ml507_dvi_clock.xaw -st ml507_dvi_clock.v +//Design Name: ml507_dvi_clock +//Device: xc5vfx70t-1ff1136 +// +// Module ml507_dvi_clock +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +// Period Jitter (unit interval) for block DCM_ADV_INST = 0.024 UI +// Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.502 ns +`timescale 1ns / 1ps + +module ml507_dvi_clock(CLKIN_IN, + CLKFX_OUT, + CLK0_OUT, + LOCKED_OUT); + + input CLKIN_IN; + output CLKFX_OUT; + output CLK0_OUT; + output LOCKED_OUT; + + wire CLKFB_IN; + wire CLKFX_BUF; + wire CLK0_BUF; + wire GND_BIT; + wire [6:0] GND_BUS_7; + wire [15:0] GND_BUS_16; + + assign GND_BIT = 0; + assign GND_BUS_7 = 7'b0000000; + assign GND_BUS_16 = 16'b0000000000000000; + assign CLK0_OUT = CLKFB_IN; + BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), + .O(CLKFX_OUT)); + BUFG CLK0_BUFG_INST (.I(CLK0_BUF), + .O(CLKFB_IN)); + DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(25), + .CLKFX_MULTIPLY(12), .CLKIN_DIVIDE_BY_2("FALSE"), + .CLKIN_PERIOD(10.000), .CLKOUT_PHASE_SHIFT("NONE"), + .DCM_AUTOCALIBRATION("TRUE"), .DCM_PERFORMANCE_MODE("MAX_SPEED"), + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), + .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), + .FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"), + .SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN), + .CLKIN(CLKIN_IN), + .DADDR(GND_BUS_7[6:0]), + .DCLK(GND_BIT), + .DEN(GND_BIT), + .DI(GND_BUS_16[15:0]), + .DWE(GND_BIT), + .PSCLK(GND_BIT), + .PSEN(GND_BIT), + .PSINCDEC(GND_BIT), + .RST(GND_BIT), + .CLKDV(), + .CLKFX(CLKFX_BUF), + .CLKFX180(), + .CLK0(CLK0_BUF), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .DO(), + .DRDY(), + .LOCKED(LOCKED_OUT), + .PSDONE()); +endmodule diff --git a/project/ise/ml507_sys_clock.v b/project/ise/ml507_sys_clock.v new file mode 100644 index 0000000..2e72fd0 --- /dev/null +++ b/project/ise/ml507_sys_clock.v @@ -0,0 +1,81 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.7 +// \ \ Application : xaw2verilog +// / / Filename : ml507_sys_clock.v +// /___/ /\ Timestamp : 05/13/2018 21:08:59 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -intstyle /repos/master/riscv_test/ipcore_dir/ml507_sys_clock.xaw -st ml507_sys_clock.v +//Design Name: ml507_sys_clock +//Device: xc5vfx70t-1ff1136 +// +// Module ml507_sys_clock +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +// Period Jitter (unit interval) for block DCM_ADV_INST = 0.010 UI +// Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.174 ns +`timescale 1ns / 1ps + +module ml507_sys_clock(CLKIN_IN, + CLKFX_OUT, + CLK0_OUT, + LOCKED_OUT); + + input CLKIN_IN; + output CLKFX_OUT; + output CLK0_OUT; + output LOCKED_OUT; + + wire CLKFB_IN; + wire CLKFX_BUF; + wire CLK0_BUF; + wire GND_BIT; + wire [6:0] GND_BUS_7; + wire [15:0] GND_BUS_16; + + assign GND_BIT = 0; + assign GND_BUS_7 = 7'b0000000; + assign GND_BUS_16 = 16'b0000000000000000; + assign CLK0_OUT = CLKFB_IN; + BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF), + .O(CLKFX_OUT)); + BUFG CLK0_BUFG_INST (.I(CLK0_BUF), + .O(CLKFB_IN)); + DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(5), + .CLKFX_MULTIPLY(3), .CLKIN_DIVIDE_BY_2("FALSE"), + .CLKIN_PERIOD(10.000), .CLKOUT_PHASE_SHIFT("NONE"), + .DCM_AUTOCALIBRATION("TRUE"), .DCM_PERFORMANCE_MODE("MAX_SPEED"), + .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"), + .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), + .FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"), + .SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN), + .CLKIN(CLKIN_IN), + .DADDR(GND_BUS_7[6:0]), + .DCLK(GND_BIT), + .DEN(GND_BIT), + .DI(GND_BUS_16[15:0]), + .DWE(GND_BIT), + .PSCLK(GND_BIT), + .PSEN(GND_BIT), + .PSINCDEC(GND_BIT), + .RST(GND_BIT), + .CLKDV(), + .CLKFX(CLKFX_BUF), + .CLKFX180(), + .CLK0(CLK0_BUF), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .DO(), + .DRDY(), + .LOCKED(LOCKED_OUT), + .PSDONE()); +endmodule diff --git a/project/ise/risc-v-workstation.xise b/project/ise/risc-v-workstation.xise index ddabd40..9918355 100644 --- a/project/ise/risc-v-workstation.xise +++ b/project/ise/risc-v-workstation.xise @@ -67,6 +67,18 @@ + + + + + + + + + + + +