79 lines
2.3 KiB
VHDL
79 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity vga is
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port(
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clk: in std_logic;
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x: out std_logic_vector(9 downto 0);
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y: out std_logic_vector(8 downto 0);
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pixel_rgb: in std_logic_vector(23 downto 0);
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dvi_d: out std_logic_vector(11 downto 0);
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dvi_hsync: out std_logic;
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dvi_vsync: out std_logic;
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dvi_de: out std_logic
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);
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end vga;
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architecture behavioral of vga is
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signal second_batch: std_logic := '0';
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signal hcount: std_logic_vector(9 downto 0) := (others => '0');
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signal vcount: std_logic_vector(8 downto 0) := (others => '0');
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signal data_enabled: std_logic;
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begin
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dvi_de <= data_enabled;
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data_enabled <= '1' when hcount < 640 and vcount < 480 else
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'0';
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dvi_hsync <= '0' when 656 <= hcount and hcount <= 720 else
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'1';
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dvi_vsync <= '0' when 483 <= vcount and vcount <= 487 else
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'1';
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x <= hcount when data_enabled = '1' and hcount < 640 else std_logic_vector(to_unsigned(639, 10));
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y <= vcount when data_enabled = '1' and vcount < 480 else std_logic_vector(to_unsigned(479, 9));
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data_output: process(clk)
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begin
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if rising_edge(clk) then
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if data_enabled = '1' then
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if second_batch = '0' then
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dvi_d <= pixel_rgb(11 downto 0);
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else
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dvi_d <= pixel_rgb(23 downto 12);
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end if;
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else
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dvi_d <= (others => '0');
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end if;
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second_batch <= not second_batch;
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end if;
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end process data_output;
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hcounter: process(clk)
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begin
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if rising_edge(clk) and second_batch = '1' then
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if hcount < 799 then
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hcount <= hcount + 1;
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else
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hcount <= (others => '0');
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end if;
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end if;
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end process hcounter;
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vcounter: process(clk, hcount)
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begin
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if rising_edge(clk) and second_batch = '1' and hcount = 700 then
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if vcount < 499 then
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vcount <= vcount + 1;
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else
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vcount <= (others => '0');
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end if;
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end if;
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end process vcounter;
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end behavioral;
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