362 lines
16 KiB
VHDL
362 lines
16 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : PS/2 interface
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-- Project :
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-------------------------------------------------------------------------------
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-- File : ps2.vhd
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-- Author : Daniel Quintero <danielqg@infonegocio.com>
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-- Company : Itoo Software
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-- Created : 2003-04-14
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-- Last update: 2003-10-30
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-- Platform : VHDL'87
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-------------------------------------------------------------------------------
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-- Description: PS/2 generic UART for mice/keyboard
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-------------------------------------------------------------------------------
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-- This code is distributed under the terms and conditions of the
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-- GNU General Public License
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2003-04-14 1.0 daniel Created
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-------------------------------------------------------------------------------
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-- URL: https://opencores.org/project,ps2core
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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entity ps2 is
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port (
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clk_i : in std_logic; -- Global clk
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rst_i : in std_logic; -- GLobal Asinchronous reset
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data_o : out std_logic_vector(7 downto 0); -- Data in
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data_i : in std_logic_vector(7 downto 0); -- Data out
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ibf_clr_i : in std_logic; -- Ifb flag clear input
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obf_set_i : in std_logic; -- Obf flag set input
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ibf_o : out std_logic; -- Received data available
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obf_o : out std_logic; -- Data ready to sent
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frame_err_o : out std_logic; -- Error receiving data
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parity_err_o : out std_logic; -- Error in received data parity
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busy_o : out std_logic; -- uart busy
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err_clr_i : in std_logic; -- Clear error flags
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wdt_o : out std_logic; -- Watchdog timer out every 400uS
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ps2_clk_io : inout std_logic; -- PS2 Clock line
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ps2_data_io : inout std_logic); -- PS2 Data line
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end ps2;
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architecture rtl of ps2 is
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type states is (idle, write_request, start, data, parity, stop);
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type debounce_states is (stable, rise, fall, wait_stable);
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--constant DEBOUNCE_TIMEOUT : integer := 200; -- clks to debounce the ps2_clk signal
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constant DEBOUNCE_BITS : integer := 8;
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--constant WATCHDOG_TIMEOUT : integer := 19200 / DEBOUNCE_TIMEOUT; -- clks to wait 400uS
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constant WATCHDOG_BITS : integer := 8;
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signal state : states;
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signal debounce_state : debounce_states;
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signal debounce_cnt : std_logic_vector(DEBOUNCE_BITS-1 downto 0);
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signal debounce_cao : std_logic;
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signal ps2_clk_syn : std_logic; -- PS2 clock input syncronized
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signal ps2_clk_clean : std_logic; -- PS2 clock debounced and clean
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signal ps2_clk_fall : std_logic; -- PS2 clock fall edge
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signal ps2_clk_rise : std_logic; -- PS2 clock rise edge
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signal ps2_data_syn : std_logic; -- PS2 data input syncronized
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signal ps2_clk_out : std_logic; -- PS2 clock output
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signal ps2_data_out : std_logic; -- PS2 clock output
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signal writing : std_logic; -- read / write cycle flag
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signal shift_cnt : std_logic_vector(2 downto 0);
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signal shift_cao : std_logic; -- Shift counter carry out
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signal shift_reg : std_logic_vector(8 downto 0);
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signal shift_in : std_logic; -- Shift register to right
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signal shift_load : std_logic; -- Shift register parallel load
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signal shift_calc_parity : std_logic; -- Shift register set parity
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signal wdt_cnt : std_logic_vector(WATCHDOG_BITS-1 downto 0);
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signal wdt_rst : std_logic; -- watchdog reset
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signal wdt_cao : std_logic; -- watchdog carry out
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signal shift_parity : std_logic; -- Current parity of shift_reg
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signal ibf : std_logic; -- IBF, In Buffer Full
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signal obf : std_logic; -- OBF, Out Buffer Full
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signal parity_err : std_logic; -- Parity error
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signal frame_err : std_logic; -- Frame error
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begin -- rtl
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-- Sincronize input signals
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syn_ps2 : process (clk_i, rst_i)
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begin
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if rst_i = '0' then -- asynchronous reset (active low)
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ps2_clk_syn <= '0';
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ps2_data_syn <= '0';
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elsif clk_i'event and clk_i = '1' then -- rising clock edge
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ps2_clk_syn <= TO_X01(ps2_clk_io);
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ps2_data_syn <= TO_X01(ps2_data_io);
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end if;
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end process syn_ps2;
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-- clk debounce timer
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debounce_count : process (clk_i, rst_i)
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begin
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if rst_i = '0' then -- asynchronous reset (active low)
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debounce_cnt <= (others => '0');
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elsif clk_i'event and clk_i = '1' then -- rising clock edge
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if (ps2_clk_fall or ps2_clk_rise or debounce_cao) = '1' then
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debounce_cnt <= (others => '0');
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else
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debounce_cnt <= debounce_cnt + 1;
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end if;
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end if;
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end process;
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debounce_cao <= debounce_cnt(DEBOUNCE_BITS-1);
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-- debounce_cao <= '1' when debounce_cnt =
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-- CONV_STD_LOGIC_VECTOR(DEBOUNCE_TIMEOUT-1, DEBOUNCE_BITS)
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-- else '0';
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-- PS2 clock debounce and edge detector
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debounce_stm : process (clk_i, rst_i)
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begin
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if rst_i = '0' then
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debounce_state <= stable;
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ps2_clk_clean <= '0';
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elsif clk_i'event and clk_i = '1' then
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case debounce_state is
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when stable =>
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if ps2_clk_clean /= ps2_clk_syn then
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if ps2_clk_syn = '1' then
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debounce_state <= rise;
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else
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debounce_state <= fall;
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end if;
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end if;
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when wait_stable =>
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if debounce_cao = '1' then
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debounce_state <= stable;
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end if;
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when rise => debounce_state <= wait_stable;
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ps2_clk_clean <= '1';
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when fall => debounce_state <= wait_stable;
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ps2_clk_clean <= '0';
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when others => null;
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end case;
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end if;
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end process;
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ps2_clk_fall <= '1' when debounce_state = fall else '0';
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ps2_clk_rise <= '1' when debounce_state = rise else '0';
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-- PS2 watchdog
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wdt_proc : process(clk_i, rst_i)
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begin
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if rst_i = '0' then -- asynchronous reset (active low)
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wdt_cnt <= (others => '0');
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elsif clk_i'event and clk_i = '1' then -- rising clock edge
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if (wdt_rst or wdt_cao) = '1' then
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wdt_cnt <= (others => '0');
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elsif debounce_cao = '1' then
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wdt_cnt <= wdt_cnt + 1;
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end if;
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end if;
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end process;
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wdt_cao <= wdt_cnt(WATCHDOG_BITS-1);
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-- wdt_cao <= '1' when wdt_cnt =
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-- CONV_STD_LOGIC_VECTOR(WATCHDOG_TIMEOUT-1, WATCHDOG_BITS)
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-- else '0';
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wdt_rst <= ps2_clk_fall;
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-- Shift register
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shift : process (clk_i, rst_i)
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begin
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if rst_i = '0' then -- asynchronous reset (active low)
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shift_reg <= (others => '0');
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elsif clk_i'event and clk_i = '1' then -- rising clock edge
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if shift_load = '1' then
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shift_reg(7 downto 0) <= data_i;
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shift_reg(8) <= '0';
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elsif shift_calc_parity = '1' then
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shift_reg(8) <= not shift_parity;
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elsif shift_in = '1' then
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shift_reg(7 downto 0) <= shift_reg(8 downto 1);
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shift_reg(8) <= ps2_data_syn;
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end if;
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end if;
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end process;
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-- Shift counter
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sft_cnt : process(clk_i, rst_i)
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begin
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if rst_i = '0' then -- asynchronous reset (active low)
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shift_cnt <= (others => '0');
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elsif clk_i'event and clk_i = '1' then -- rising clock edge
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if state = start then
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shift_cnt <= (others => '0');
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elsif state = data and ps2_clk_fall = '1' then
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shift_cnt <= shift_cnt + 1;
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end if;
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end if;
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end process;
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shift_cao <= '1' when shift_cnt = "111" else '0';
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-- Odd Parity generator
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shift_parity <= (shift_reg(0) xor
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shift_reg(1) xor
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shift_reg(2) xor
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shift_reg(3) xor
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shift_reg(4) xor
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shift_reg(5) xor
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shift_reg(6) xor
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shift_reg(7));
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-- Main State Machine
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stm : process (clk_i, rst_i)
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begin
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if rst_i = '0' then -- asynchronous reset (active low)
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state <= idle;
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writing <= '0';
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elsif clk_i'event and clk_i = '1' then -- rising clock edge
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case state is
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-- Waiting for clk
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when idle => if obf_set_i = '1' and writing = '0' then
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state <= write_request;
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writing <= '1';
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elsif ps2_clk_fall = '1' then
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state <= start;
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end if;
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-- Write request, clk low
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when write_request => if wdt_cao = '1' then
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state <= idle;
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end if;
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-- Clock 1, start bit
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when start => if wdt_cao = '1' then
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state <= idle;
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elsif ps2_clk_fall = '1' then
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state <= data;
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end if;
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-- Clocks 2-9, Data bits (LSB first)
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when data => if wdt_cao = '1' then
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state <= idle;
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elsif ps2_clk_fall = '1' and
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shift_cao = '1' then
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state <= parity;
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end if;
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-- Clock 10, Parity bit
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when parity => if wdt_cao = '1' then
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state <= idle;
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elsif ps2_clk_fall = '1' then
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state <= stop;
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end if;
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-- Clock 11, Stop bit
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when stop => writing <= '0';
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state <= idle;
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when others => null;
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end case;
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end if;
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end process;
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-- State flags
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flags_proc : process (clk_i, rst_i, state, writing)
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begin -- process stm_out
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-- Input Buffer write flag
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if rst_i = '0' then -- asynchronous reset (active low)
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--obf <= '0';
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ibf <= '0';
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parity_err <= '0';
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frame_err <= '0';
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elsif clk_i'event and clk_i = '1' then -- rising clock edge
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-- Parity error flag
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if err_clr_i = '1' then
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parity_err <= '0';
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elsif writing = '0' and state = stop then
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if shift_reg(8) /= not shift_parity then
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parity_err <= '1';
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end if;
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end if;
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-- Frame error flag
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if err_clr_i = '1' then
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frame_err <= '0';
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elsif (state = start or
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state = data or state = parity) and wdt_cao = '1' then
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frame_err <= '1';
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end if;
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-- Input Buffer full flag
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if ibf_clr_i = '1' then
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ibf <= '0';
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elsif writing = '0' and state = stop then
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if shift_reg(8) = not shift_parity then
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ibf <= '1';
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end if;
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end if;
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-- Output buffer full flag
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--if state = stop and writing = '1' then
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-- obf <= '0';
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--elsif obf_set_i = '1' then
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-- obf <= '1';
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--end if;
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end if;
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end process;
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obf <= writing;
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-- Shift register control
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shift_load <= '1' when obf_set_i = '1' else '0';
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shift_calc_parity <= '1' when state = idle and writing = '1' else '0';
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shift_in <= ps2_clk_fall when state = data or state = start else '0';
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-- PS2 Registered outputs
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syn_ps2_out : process (clk_i, rst_i)
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begin
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if rst_i = '0' then -- asynchronous reset (active low)
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ps2_data_out <= '1';
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ps2_clk_out <= '1';
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elsif clk_i'event and clk_i = '1' then -- rising clock edge
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-- PS2 Data out
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if writing = '1' then
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if state = idle then
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ps2_data_out <= '0';
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elsif state = data or state = start then
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ps2_data_out <= shift_reg(0);
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else
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ps2_data_out <= '1';
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end if;
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end if;
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-- PS2 Clk out
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if state = write_request then
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ps2_clk_out <= '0';
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else
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ps2_clk_out <= '1';
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end if;
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end if;
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end process;
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data_o <= shift_reg(7 downto 0);
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ibf_o <= ibf;
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obf_o <= obf;
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busy_o <= '0' when state = idle and writing = '0' else '1';
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parity_err_o <= parity_err;
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frame_err_o <= frame_err;
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wdt_o <= wdt_cao;
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ps2_clk_io <= '0' when ps2_clk_out = '0' else 'Z';
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ps2_data_io <= '0' when ps2_data_out = '0' else 'Z';
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end rtl;
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