151 lines
4.9 KiB
VHDL
151 lines
4.9 KiB
VHDL
library ieee;
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library unisim;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity init_ch7301c is
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generic (
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input_clk: integer;
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address: std_logic_vector(6 downto 0) := "1110110" -- 0x76
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);
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port (
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clk: in std_logic;
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reset: in std_logic;
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finished: out std_logic;
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error: out std_logic;
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i2c_scl: inout std_logic;
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i2c_sda: inout std_logic;
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dvi_reset: out std_logic
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);
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end init_ch7301c;
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architecture Behavioral of init_ch7301c is
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signal i2c_reset: std_logic := '1';
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signal i2c_execute: std_logic := '0';
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signal i2c_busy: std_logic;
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signal i2c_busy_old: std_logic;
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signal i2c_address: std_logic_vector(6 downto 0);
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signal i2c_write: std_logic;
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signal i2c_data_in: std_logic_vector(7 downto 0);
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signal i2c_data_out: std_logic_vector(7 downto 0);
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signal i2c_error: std_logic;
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begin
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i2c_master: entity work.i2c_master generic map (
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input_clk => input_clk,
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bus_clk => 100_000
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) port map (
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clk => clk,
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reset_n => i2c_reset,
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ena => i2c_execute,
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addr => i2c_address,
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rw => not i2c_write,
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data_wr => i2c_data_in,
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busy => i2c_busy,
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data_rd => i2c_data_out,
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ack_error => i2c_error,
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scl => i2c_scl,
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sda => i2c_sda
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);
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main: process(clk, reset)
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-- ch7301c needs some time (>2µs) to init its i2c port after reset
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constant max_delay: integer := input_clk / 200_000; -- 5µs
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variable delay: integer range 0 to max_delay := 0;
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variable busy_count: integer range 0 to 12 := 0;
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begin
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if reset = '1' then
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delay := 0;
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busy_count := 0;
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finished <= '0';
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error <= '0';
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-- reset components
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dvi_reset <= '0';
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i2c_execute <= '0';
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i2c_reset <= '0';
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elsif rising_edge(clk) then
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if delay = 5 then
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-- init components
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dvi_reset <= '1';
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i2c_reset <= '1';
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delay := delay + 1;
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elsif delay = max_delay then
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i2c_busy_old <= i2c_busy; -- remember old value
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if i2c_busy_old = '0' and i2c_busy = '1' then
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-- count rising edges on i2c_busy:
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-- command was accepted, ready for new one
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busy_count := busy_count + 1;
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end if;
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if i2c_error = '1' then
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-- abort on error
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i2c_execute <= '0';
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error <= '1';
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busy_count := 3;
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end if;
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case busy_count is
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when 0 =>
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-- start configure sequence
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i2c_execute <= '1';
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i2c_write <= '1';
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i2c_address <= address;
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-- select register PM (power management)
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i2c_data_in <= x"49";
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when 1 =>
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-- enable clock pll, dvi encoder and transmitter
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i2c_data_in <= x"C0";
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when 2 =>
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-- select register DC (DAC control)
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i2c_data_in <= x"21";
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when 3 =>
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-- enable dac bypass and h/vsync outputs
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i2c_data_in <= x"09";
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when 4 =>
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-- select register TPCP (PLL charge pump control)
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i2c_data_in <= x"33";
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when 5 =>
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-- enable <= 65 MHz mode (datasheet table 10)
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i2c_data_in <= x"08";
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when 6 =>
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-- select register TPD (PLL divider)
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i2c_data_in <= x"34";
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when 7 =>
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-- enable <= 65 MHz mode (datasheet table 10)
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i2c_data_in <= x"16";
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when 8 =>
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-- select register TPF (PLL filter)
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i2c_data_in <= x"36";
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when 9 =>
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-- enable <= 65 MHz mode (datasheet table 10)
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i2c_data_in <= x"60";
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when 10 =>
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-- select register CM (clock mode)
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i2c_data_in <= x"1C";
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when 11 =>
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-- enable singledual edge clocking mode
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-- single: 01, dual: 00 (default)
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i2c_data_in <= x"01";
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when 12 =>
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-- no more commands
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i2c_execute <= '0';
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finished <= '1';
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end case;
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else
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delay := delay + 1;
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end if;
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end if;
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end process main;
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end Behavioral;
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