library ieee;
library unisim;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- Xilinx primitives (obufds)
use unisim.VComponents.all;

entity terminal is
    generic (
        clk_f: integer
    );
    port (
        clk: in std_logic;
        reset: in std_logic;

        write_enable: in std_logic;
        write_data: in std_logic_vector(7 downto 0);

        dvi_d: out std_logic_vector(11 downto 0);
        dvi_clk_p: out std_logic;
        dvi_clk_n: out std_logic;
        dvi_hsync: out std_logic;
        dvi_vsync: out std_logic;
        dvi_de: out std_logic;
        dvi_reset: out std_logic;
        i2c_scl: inout std_logic;
        i2c_sda: inout std_logic
    );
end terminal;

architecture syn of terminal is
    signal image_x: std_logic_vector(9 downto 0);
    signal image_y: std_logic_vector(8 downto 0);
    signal pixel_rgb: std_logic_vector(23 downto 0);

    signal fb_write_enable: std_logic;
    signal fb_write_address: std_logic_vector(12 downto 0);
    signal fb_write_data: std_logic_vector(7 downto 0);

    signal write_x: unsigned(6 downto 0);
    signal write_y: unsigned(5 downto 0);
begin

    fb_write_address <= std_logic_vector(write_x) & std_logic_vector(write_y);

    process(clk)
        variable next_line: unsigned(5 downto 0);
    begin
        if rising_edge(clk) then
            fb_write_enable <= '0';
            fb_write_data <= write_data;

            -- calculate next line
            if write_y = 59 then
                next_line := (others => '0');
            else
                next_line := write_y + 1;
            end if;

            if write_enable = '1' then
                fb_write_enable <= '1';
                if write_x = 79 then
                    write_x <= (others => '0');
                    write_y <= next_line;
                else
                    write_x <= write_x + 1;
                end if;

                -- carriage return
                if write_data = x"0d" then
                    fb_write_enable <= '0';
                    write_x <= (others => '0');
                end if;

                -- line feed (implicit CR)
                if write_data = x"0a" then
                    fb_write_enable <= '0';
                    write_x <= (others => '0');
                    write_y <= next_line;
                end if;
            end if;
        end if;
    end process;

    dvi_clk_ds: obufds port map (
        I => clk,
        O => dvi_clk_p,
        OB => dvi_clk_n
    );

    init_ch7301c: entity work.init_ch7301c generic map (
        input_clk => clk_f
    ) port map (
        clk => clk,
        reset => reset,
        finished => open,
        error => open,
        i2c_scl => i2c_scl,
        i2c_sda => i2c_sda,
        dvi_reset => dvi_reset
    );

    vga: entity work.vga port map (
        clk => clk,
        x => image_x,
        y => image_y,
        pixel_rgb => pixel_rgb,
        dvi_d => dvi_d,
        dvi_hsync => dvi_hsync,
        dvi_vsync => dvi_vsync,
        dvi_de => dvi_de
    );

    framebuffer: entity work.framebuffer generic map (
        input_clk => clk_f
    ) port map (
        clk => clk,
        x => image_x,
        y => image_y,
        rgb => pixel_rgb,
        write_enable => fb_write_enable,
        write_address => fb_write_address,
        write_data => fb_write_data
    );

end syn;