library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity main is
    port (
        clk: in std_logic;

        dvi_d: out std_logic_vector(11 downto 0);
        dvi_clk_p: out std_logic;
        dvi_clk_n: out std_logic;
        dvi_hsync: out std_logic;
        dvi_vsync: out std_logic;
        dvi_de: out std_logic;
        dvi_reset: out std_logic;
        i2c_scl: inout std_logic;
        i2c_sda: inout std_logic;

        ps2_scl: inout std_logic;
        ps2_sda: inout std_logic;

        switch_center: in std_logic;
        rotary_up: in std_logic;
        rotary_down: in std_logic;
        rotary_push: in std_logic;

        led: out std_logic_vector(7 downto 0)
    );
end main;

architecture syn of main is
    constant clk_vga_f: integer := 48_000_000;
    signal clk_vga: std_logic;

    signal reset: std_logic;

    signal write_enable: std_logic;
    signal write_data: std_logic_vector(7 downto 0);
begin

    reset <= switch_center;

    -- convert the 100MHz to a 48MHz pixel clock
    clock_source: entity work.clock_source port map (
		CLKIN_IN => clk,
		CLKFX_OUT => clk_vga
	);

    terminal: entity work.terminal port map (
        clk => clk_vga,
        reset => reset,
        write_enable => write_enable,
        write_data => write_data,
        dvi_d => dvi_d,
        dvi_clk_p => dvi_clk_p,
        dvi_clk_n => dvi_clk_n,
        dvi_hsync => dvi_hsync,
        dvi_vsync => dvi_vsync,
        dvi_de => dvi_de,
        dvi_reset => dvi_reset,
        i2c_scl => i2c_scl,
        i2c_sda => i2c_sda
    );

    -- write an example text pattern to test the terminal
    process(clk_vga, reset)
        variable delay: integer range 0 to 300_000;
        variable line: integer range 0 to 90;
        variable max: integer range 0 to 90;
    begin
        if reset = '1' then
            delay := 0;
            line := 0;
            max := 0;
        elsif rising_edge(clk_vga) then
            write_enable <= '0';

            if delay = 300_000 then
                write_enable <= '1';
                write_data <= "0" & std_logic_vector(to_unsigned(33 + line, 7));

                if line = max then
                    write_data <= x"0a";
                    line := 0;
                    if max = 90 then
                        max := 0;
                    else
                        max := max + 1;
                    end if;
                else
                    line := line + 1;
                end if;

                delay := 0;
            else
                delay := delay + 1;
            end if;
        end if;
    end process;

    keyboard_i: entity work.keyboard generic map (
        input_clk => clk_vga_f
    ) port map (
        clk => clk_vga,
        reset => reset,
        bytes_received => led(5 downto 0),
        ps2_scl => ps2_scl,
        ps2_sda => ps2_sda
    );

    led(7) <= reset;
    led(6) <= '0';

end syn;